mirror of https://github.com/YosysHQ/yosys.git
Refactor ice40_dsp.pmg
This commit is contained in:
Eddie Hung
parent
0020a18929
commit
c8310a6e76
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@ -31,12 +31,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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#if 1
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
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log("addAB: %s\n", log_id(st.addAB, "--"));
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log("muxAB: %s\n", log_id(st.muxAB, "--"));
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log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--"));
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log("add: %s\n", log_id(st.add, "--"));
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log("mux: %s\n", log_id(st.mux, "--"));
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log("ffO: %s\n", log_id(st.ffO, "--"));
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#endif
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@ -146,10 +146,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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SigSpec O = st.sigO;
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int O_width = GetSize(O);
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if (O_width == 33) {
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log_assert(st.addAB);
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log_assert(st.add);
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// If we have a signed multiply-add, then perform sign extension
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// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
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if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
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if (st.add->getParam("\\A_SIGNED").as_bool() && st.add->getParam("\\B_SIGNED").as_bool())
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pm.module->connect(O[32], O[31]);
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else
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cell->setPort("\\CO", O[32]);
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@ -164,18 +164,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setPort("\\O", O);
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bool accum = false;
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if (st.addAB) {
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if (st.addA)
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accum = (st.ffO && st.addAB->getPort("\\B") == st.sigO);
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else if (st.addB)
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accum = (st.ffO && st.addAB->getPort("\\A") == st.sigO);
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else log_abort();
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if (st.add) {
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accum = (st.ffO && st.add->getPort(st.addAB == "\\A" ? "\\B" : "\\A") == st.sigO);
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if (accum)
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log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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log(" accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
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else
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log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
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cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
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log(" adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
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cell->setPort("\\ADDSUBTOP", st.add->type == "$add" ? State::S0 : State::S1);
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cell->setPort("\\ADDSUBBOT", st.add->type == "$add" ? State::S0 : State::S1);
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} else {
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cell->setPort("\\ADDSUBTOP", State::S0);
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cell->setPort("\\ADDSUBBOT", State::S0);
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@ -188,10 +184,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setPort("\\OHOLDBOT", State::S0);
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SigSpec acc_reset = State::S0;
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if (st.muxA)
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acc_reset = st.muxA->getPort("\\S");
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if (st.muxB)
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acc_reset = pm.module->Not(NEW_ID, st.muxB->getPort("\\S"));
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if (st.mux) {
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if (st.muxAB == "\\A")
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acc_reset = st.mux->getPort("\\S");
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else
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acc_reset = pm.module->Not(NEW_ID, st.mux->getPort("\\S"));
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}
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cell->setPort("\\OLOADTOP", acc_reset);
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cell->setPort("\\OLOADBOT", acc_reset);
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@ -219,8 +217,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
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if (st.ffO) {
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if (st.ffO_lo)
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
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if (st.o_lo)
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
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else
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cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
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@ -228,8 +226,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
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}
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else {
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
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cell->setParam("\\BOTOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
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cell->setParam("\\BOTOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
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}
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if (cell != st.mul)
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@ -237,7 +235,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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else
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pm.blacklist(st.mul);
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pm.autoremove(st.ffFJKG);
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pm.autoremove(st.addAB);
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pm.autoremove(st.add);
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}
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struct Ice40DspPass : public Pass {
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@ -249,6 +247,7 @@ struct Ice40DspPass : public Pass {
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log(" ice40_dsp [options] [selection]\n");
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log("\n");
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log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
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log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -1,9 +1,25 @@
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pattern ice40_dsp
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state <SigBit> clock
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state <bool> clock_pol cd_signed
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state <bool> clock_pol cd_signed o_lo
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state <SigSpec> sigA sigB sigCD sigH sigO
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state <Cell*> addAB muxAB
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state <Cell*> add mux
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state <IdString> addAB muxAB
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state <bool> ffAcepol ffBcepol ffCDcepol ffOcepol
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state <bool> ffArstpol ffBrstpol ffCDrstpol ffFJKGrstpol ffOrstpol
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state <Cell*> ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux ffCDrstmux
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state <Cell*> ffFJKG ffFJKGrstmux ffO ffOcemux ffOrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol dffclock_pol
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match mul
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select mul->type.in($mul, \SB_MAC16)
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@ -47,122 +63,108 @@ code sigA sigB sigH
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log_assert(nusers(O.extract_end(i)) <= 1);
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endcode
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match ffA
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if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
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select ffA->type.in($dff)
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffA, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code sigA clock clock_pol
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if (ffA) {
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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clock = port(ffA, \CLK).as_bit();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux) {
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ffArstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffAcemux = dffcemux;
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ffAcepol = dffcepol;
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}
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sigA = dffD;
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}
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}
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endcode
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match ffB
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if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
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select ffB->type.in($dff)
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filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
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slice offset GetSize(port(ffB, \Q))
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filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
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optional
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endmatch
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code sigB clock clock_pol
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if (ffB) {
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffB, \CLK).as_bit();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol
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if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux) {
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ffBrstmux = dffrstmux;
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ffBrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffBcemux = dffcemux;
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ffBcepol = dffcepol;
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}
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sigB = dffD;
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}
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}
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endcode
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match ffFJKG
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// Ensure pipeline register is not already used
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if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
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select ffFJKG->type.in($dff)
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select nusers(port(ffFJKG, \D)) == 2
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index <SigSpec> port(ffFJKG, \D) === sigH
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optional
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endmatch
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code sigH sigO clock clock_pol
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if (ffFJKG) {
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sigH = port(ffFJKG, \Q);
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for (auto b : sigH)
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if (b.wire->get_bool_attribute(\keep))
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code argD ffFJKG ffFJKGrstmux ffFJKGrstpol sigH sigO clock clock_pol
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if (nusers(sigH) == 2 &&
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(mul->type != \SB_MAC16 ||
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(!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool()))) {
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argD = sigH;
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subpattern(out_dffe);
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if (dff) {
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ffFJKG = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux) {
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ffFJKGrstmux = dffrstmux;
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ffFJKGrstpol = dffrstpol;
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}
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// F/J/K/G do not have a CE-like (hold) input
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if (dffcemux)
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reject;
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SigBit c = port(ffFJKG, \CLK).as_bit();
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bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
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// Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
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// shared with A and B
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if ((ffArstmux != NULL) != (ffFJKGrstmux != NULL))
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reject;
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if ((ffBrstmux != NULL) != (ffFJKGrstmux != NULL))
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reject;
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if (ffArstmux) {
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if (port(ffArstmux, \S) != port(ffFJKGrstmux, \S))
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reject;
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if (ffArstpol != ffFJKGrstpol)
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reject;
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}
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if (ffBrstmux) {
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if (port(ffBrstmux, \S) != port(ffFJKGrstmux, \S))
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reject;
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if (ffBrstpol != ffFJKGrstpol)
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reject;
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}
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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sigH = dffQ;
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}
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}
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sigO = sigH;
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endcode
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match addA
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select addA->type.in($add)
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select nusers(port(addA, \A)) == 2
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filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
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//index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
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filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int())
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match add
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if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
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select add->type.in($add)
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choice <IdString> AB {\A, \B}
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select nusers(port(add, AB)) == 2
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index <SigBit> port(add, AB)[0] === sigH[0]
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filter GetSize(port(add, AB)) <= GetSize(sigH)
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filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
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set addAB AB
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optional
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endmatch
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match addB
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if !addA
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select addB->type.in($add, $sub)
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select nusers(port(addB, \B)) == 2
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filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
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//index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
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filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int())
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optional
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endmatch
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code addAB sigCD sigO cd_signed
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if (addA) {
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addAB = addA;
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sigCD = port(addAB, \B);
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cd_signed = param(addAB, \B_SIGNED).as_bool();
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}
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else if (addB) {
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addAB = addB;
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sigCD = port(addAB, \A);
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cd_signed = param(addAB, \A_SIGNED).as_bool();
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}
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if (addAB) {
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if (mul->type == \SB_MAC16) {
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// Ensure that adder is not used
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if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
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param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
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reject;
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}
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code sigCD sigO cd_signed
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if (add) {
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sigCD = port(add, addAB == \A ? \B : \A);
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cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
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int natural_mul_width = GetSize(sigA) + GetSize(sigB);
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int actual_mul_width = GetSize(sigH);
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@ -171,97 +173,75 @@ code addAB sigCD sigO cd_signed
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if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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reject;
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// If accumulator, check adder width and signedness
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if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
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if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
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reject;
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sigO = port(addAB, \Y);
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sigO = port(add, \Y);
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}
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endcode
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match muxA
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select muxA->type.in($mux)
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index <int> nusers(port(muxA, \A)) === 2
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index <SigSpec> port(muxA, \A) === sigO
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match mux
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select mux->type == $mux
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choice <IdString> AB {\A, \B}
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index <int> nusers(port(mux, AB)) === 2
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index <SigSpec> port(mux, AB) === sigO
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set muxAB AB
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optional
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endmatch
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match muxB
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if !muxA
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select muxB->type.in($mux)
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index <int> nusers(port(muxB, \B)) === 2
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index <SigSpec> port(muxB, \B) === sigO
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optional
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endmatch
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code muxAB sigO
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if (muxA)
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muxAB = muxA;
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else if (muxB)
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muxAB = muxB;
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||||
if (muxAB)
|
||||
sigO = port(muxAB, \Y);
|
||||
code sigO
|
||||
if (mux)
|
||||
sigO = port(mux, \Y);
|
||||
endcode
|
||||
|
||||
match ffO
|
||||
// Ensure that register is not already used
|
||||
if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
|
||||
// Ensure that OLOADTOP/OLOADBOT is unused or zero
|
||||
if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
|
||||
if nusers(sigO) == 2
|
||||
select ffO->type.in($dff)
|
||||
filter GetSize(port(ffO, \D)) >= GetSize(sigO)
|
||||
slice offset GetSize(port(ffO, \D))
|
||||
filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
|
||||
optional
|
||||
endmatch
|
||||
code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
|
||||
if (mul->type != \SB_MAC16 ||
|
||||
// Ensure that register is not already used
|
||||
((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) &&
|
||||
// Ensure that OLOADTOP/OLOADBOT is unused or zero
|
||||
(mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero()))) {
|
||||
|
||||
match ffO_lo
|
||||
if !ffO && GetSize(sigO) > 16
|
||||
// Ensure that register is not already used
|
||||
if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
|
||||
// Ensure that OLOADTOP/OLOADBOT is unused or zero
|
||||
if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
|
||||
if nusers(sigO.extract(0, 16)) == 2
|
||||
select ffO_lo->type.in($dff)
|
||||
filter GetSize(port(ffO_lo, \D)) >= 16
|
||||
slice offset GetSize(port(ffO_lo, \D))
|
||||
filter offset+GetSize(sigO) <= GetSize(port(ffO_lo, \D)) && port(ffO_lo, \D).extract(offset, 16) == sigO.extract(0, 16)
|
||||
optional
|
||||
endmatch
|
||||
dff = nullptr;
|
||||
|
||||
code ffO clock clock_pol sigO sigCD cd_signed
|
||||
if (ffO_lo) {
|
||||
log_assert(!ffO);
|
||||
ffO = ffO_lo;
|
||||
}
|
||||
if (ffO) {
|
||||
for (auto b : port(ffO, \Q))
|
||||
if (b.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
// First try entire sigO
|
||||
if (nusers(sigO) == 2) {
|
||||
argD = sigO;
|
||||
subpattern(out_dffe);
|
||||
}
|
||||
|
||||
SigBit c = port(ffO, \CLK).as_bit();
|
||||
bool cp = param(ffO, \CLK_POLARITY).as_bool();
|
||||
// Otherwise try just its least significant 16 bits
|
||||
if (!dff && GetSize(sigO) > 16) {
|
||||
argD = sigO.extract(0, 16);
|
||||
if (nusers(argD) == 2) {
|
||||
subpattern(out_dffe);
|
||||
o_lo = dff;
|
||||
}
|
||||
}
|
||||
|
||||
if (clock != SigBit() && (c != clock || cp != clock_pol))
|
||||
reject;
|
||||
if (dff) {
|
||||
ffO = dff;
|
||||
clock = dffclock;
|
||||
clock_pol = dffclock_pol;
|
||||
if (dffrstmux) {
|
||||
ffOrstmux = dffrstmux;
|
||||
ffOrstpol = dffrstpol;
|
||||
}
|
||||
if (dffcemux) {
|
||||
ffOcemux = dffcemux;
|
||||
ffOcepol = dffcepol;
|
||||
}
|
||||
|
||||
clock = c;
|
||||
clock_pol = cp;
|
||||
|
||||
sigO.replace(port(ffO, \D), port(ffO, \Q));
|
||||
sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
|
||||
}
|
||||
|
||||
// Loading value into output register is not
|
||||
// supported unless using accumulator
|
||||
if (muxAB) {
|
||||
if (mux) {
|
||||
if (sigCD != sigO)
|
||||
reject;
|
||||
if (muxA)
|
||||
sigCD = port(muxAB, \B);
|
||||
else if (muxB)
|
||||
sigCD = port(muxAB, \A);
|
||||
else log_abort();
|
||||
sigCD = port(mux, muxAB == \B ? \A : \B);
|
||||
|
||||
cd_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
|
||||
cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
|
||||
}
|
||||
}
|
||||
sigCD.extend_u0(32, cd_signed);
|
||||
|
|
@ -270,3 +250,256 @@ endcode
|
|||
code
|
||||
accept;
|
||||
endcode
|
||||
|
||||
// #######################
|
||||
|
||||
subpattern in_dffe
|
||||
arg argD argQ clock clock_pol
|
||||
|
||||
code
|
||||
dff = nullptr;
|
||||
for (auto c : argQ.chunks()) {
|
||||
if (!c.wire)
|
||||
reject;
|
||||
if (c.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
}
|
||||
endcode
|
||||
|
||||
match ff
|
||||
select ff->type.in($dff)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \Q)[offset] === argQ[0]
|
||||
|
||||
// Check that the rest of argQ is present
|
||||
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
|
||||
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
||||
|
||||
set ffoffset offset
|
||||
endmatch
|
||||
|
||||
code argQ argD
|
||||
{
|
||||
if (clock != SigBit()) {
|
||||
if (port(ff, \CLK) != clock)
|
||||
reject;
|
||||
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
|
||||
reject;
|
||||
}
|
||||
|
||||
SigSpec Q = port(ff, \Q);
|
||||
dff = ff;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
|
||||
dffD = argQ;
|
||||
argD = port(ff, \D);
|
||||
argQ = Q;
|
||||
dffD.replace(argQ, argD);
|
||||
// Only search for ffrstmux if dffD only
|
||||
// has two (ff, ffrstmux) users
|
||||
if (nusers(dffD) > 2)
|
||||
argD = SigSpec();
|
||||
}
|
||||
endcode
|
||||
|
||||
match ffrstmux
|
||||
if !argD.empty()
|
||||
select ffrstmux->type.in($mux)
|
||||
index <SigSpec> port(ffrstmux, \Y) === argD
|
||||
|
||||
choice <IdString> BA {\B, \A}
|
||||
// DSP48E1 only supports reset to zero
|
||||
select port(ffrstmux, BA).is_fully_zero()
|
||||
|
||||
define <bool> pol (BA == \B)
|
||||
set ffrstpol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD
|
||||
if (ffrstmux) {
|
||||
dffrstmux = ffrstmux;
|
||||
dffrstpol = ffrstpol;
|
||||
argD = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
dffD.replace(port(ffrstmux, \Y), argD);
|
||||
|
||||
// Only search for ffcemux if argQ has at
|
||||
// least 3 users (ff, <upstream>, ffrstmux) and
|
||||
// dffD only has two (ff, ffrstmux)
|
||||
if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
|
||||
argD = SigSpec();
|
||||
}
|
||||
else
|
||||
dffrstmux = nullptr;
|
||||
endcode
|
||||
|
||||
match ffcemux
|
||||
if !argD.empty()
|
||||
select ffcemux->type.in($mux)
|
||||
index <SigSpec> port(ffcemux, \Y) === argD
|
||||
choice <IdString> AB {\A, \B}
|
||||
index <SigSpec> port(ffcemux, AB) === argQ
|
||||
define <bool> pol (AB == \A)
|
||||
set ffcepol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD
|
||||
if (ffcemux) {
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
argD = port(ffcemux, ffcepol ? \B : \A);
|
||||
dffD.replace(port(ffcemux, \Y), argD);
|
||||
}
|
||||
else
|
||||
dffcemux = nullptr;
|
||||
endcode
|
||||
|
||||
// #######################
|
||||
|
||||
subpattern out_dffe
|
||||
arg argD argQ clock clock_pol
|
||||
|
||||
code
|
||||
dff = nullptr;
|
||||
endcode
|
||||
|
||||
match ffcemux
|
||||
select ffcemux->type.in($mux)
|
||||
// ffcemux output must have two users: ffcemux and ff.D
|
||||
select nusers(port(ffcemux, \Y)) == 2
|
||||
|
||||
choice <IdString> AB {\A, \B}
|
||||
// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
|
||||
select nusers(port(ffcemux, AB)) >= 3
|
||||
|
||||
slice offset GetSize(port(ffcemux, \Y))
|
||||
define <IdString> BA (AB == \A ? \B : \A)
|
||||
index <SigBit> port(ffcemux, BA)[offset] === argD[0]
|
||||
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(BA) >= offset + GetSize(argD)
|
||||
filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
|
||||
|
||||
set ffoffset offset
|
||||
define <bool> pol (BA == \B)
|
||||
set ffcepol pol
|
||||
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD argQ
|
||||
dffcemux = ffcemux;
|
||||
if (ffcemux) {
|
||||
SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
|
||||
if (ffoffset + GetSize(argD) > GetSize(BA))
|
||||
reject;
|
||||
for (int i = 1; i < GetSize(argD); i++)
|
||||
if (BA[ffoffset+i] != argD[i])
|
||||
reject;
|
||||
|
||||
SigSpec Y = port(ffcemux, \Y);
|
||||
argQ = argD;
|
||||
argD.replace(BA, Y);
|
||||
argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
|
||||
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
}
|
||||
endcode
|
||||
|
||||
match ffrstmux
|
||||
select ffrstmux->type.in($mux)
|
||||
// ffrstmux output must have two users: ffrstmux and ff.D
|
||||
select nusers(port(ffrstmux, \Y)) == 2
|
||||
|
||||
choice <IdString> BA {\B, \A}
|
||||
// DSP48E1 only supports reset to zero
|
||||
select port(ffrstmux, BA).is_fully_zero()
|
||||
|
||||
slice offset GetSize(port(ffrstmux, \Y))
|
||||
define <IdString> AB (BA == \B ? \A : \B)
|
||||
index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
|
||||
|
||||
// Check that offset is consistent
|
||||
filter !ffcemux || ffoffset == offset
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(AB) >= offset + GetSize(argD)
|
||||
filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
|
||||
|
||||
set ffoffset offset
|
||||
define <bool> pol (AB == \A)
|
||||
set ffrstpol pol
|
||||
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD argQ
|
||||
dffrstmux = ffrstmux;
|
||||
if (ffrstmux) {
|
||||
SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
SigSpec Y = port(ffrstmux, \Y);
|
||||
argD.replace(AB, Y);
|
||||
|
||||
dffrstmux = ffrstmux;
|
||||
dffrstpol = ffrstpol;
|
||||
}
|
||||
endcode
|
||||
|
||||
match ff
|
||||
select ff->type.in($dff)
|
||||
// DSP48E1 does not support clock inversion
|
||||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigBit> port(ff, \D)[offset] === argD[0]
|
||||
|
||||
// Check that offset is consistent
|
||||
filter (!ffcemux && !ffrstmux) || ffoffset == offset
|
||||
// Check that the rest of argD is present
|
||||
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
|
||||
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
|
||||
// Check that FF.Q is connected to CE-mux
|
||||
filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
||||
|
||||
set ffoffset offset
|
||||
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argQ
|
||||
if (ff) {
|
||||
if (clock != SigBit()) {
|
||||
if (port(ff, \CLK) != clock)
|
||||
reject;
|
||||
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
|
||||
reject;
|
||||
}
|
||||
|
||||
SigSpec D = port(ff, \D);
|
||||
SigSpec Q = port(ff, \Q);
|
||||
if (!ffcemux) {
|
||||
argQ = argD;
|
||||
argQ.replace(D, Q);
|
||||
}
|
||||
|
||||
for (auto c : argQ.chunks()) {
|
||||
if (c.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
Const init = c.wire->attributes.at(\init, State::Sx);
|
||||
if (!init.is_fully_undef() && !init.is_fully_zero())
|
||||
reject;
|
||||
}
|
||||
|
||||
dff = ff;
|
||||
dffQ = argQ;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
|
||||
}
|
||||
// No enable/reset mux possible without flop
|
||||
else if (dffcemux || dffrstmux)
|
||||
reject;
|
||||
endcode
|
||||
|
|
|
|||
Loading…
Reference in New Issue