mirror of https://github.com/YosysHQ/yosys.git
Add support for A/B/C/D/AD reset
This commit is contained in:
Eddie Hung
parent
6a95ecd41d
commit
0d709d2bb5
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@ -257,25 +257,16 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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#if 1
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log("\n");
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log("preAdd: %s\n", log_id(st.preAdd, "--"));
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log("ffAD: %s\n", log_id(st.ffAD, "--"));
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log("ffADmux: %s\n", log_id(st.ffADmux, "--"));
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("ffBmux: %s\n", log_id(st.ffBmux, "--"));
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log("ffC: %s\n", log_id(st.ffC, "--"));
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log("ffCmux: %s\n", log_id(st.ffCmux, "--"));
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log("ffD: %s\n", log_id(st.ffD, "--"));
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log("ffDmux: %s\n", log_id(st.ffDmux, "--"));
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log("ffAD: %s %s %s\n", log_id(st.ffAD, "--"), log_id(st.ffADcemux, "--"), log_id(st.ffADrstmux, "--"));
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
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log("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
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log("ffD: %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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log("ffMcemux: %s\n", log_id(st.ffMcemux, "--"));
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log("ffMrstmux: %s\n", log_id(st.ffMrstmux, "--"));
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log("ffM: %s %s %s\n", log_id(st.ffM, "--"), log_id(st.ffMcemux, "--"), log_id(st.ffMrstmux, "--"));
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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log("ffPcemux: %s\n", log_id(st.ffPcemux, "--"));
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log("ffPrstmux: %s\n", log_id(st.ffPrstmux, "--"));
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log("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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#endif
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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@ -297,8 +288,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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cell->connections_.at("\\INMODE") = Const::from_string("00100");
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if (st.ffAD) {
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if (st.ffADmux) {
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SigSpec S = st.ffADmux->getPort("\\S");
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if (st.ffADcemux) {
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SigSpec S = st.ffADcemux->getPort("\\S");
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cell->setPort("\\CEAD", st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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@ -341,80 +332,46 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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{
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cell->setPort("\\CLK", st.clock);
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if (st.ffA) {
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SigSpec A = cell->getPort("\\A");
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SigSpec D = st.ffA->getPort("\\D");
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SigSpec Q = pm.sigmap(st.ffA->getPort("\\Q"));
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auto f = [&pm,cell](IdString port, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
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SigSpec A = cell->getPort(port);
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SigSpec D = ff->getPort("\\D");
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SigSpec Q = pm.sigmap(ff->getPort("\\Q"));
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A.replace(Q, D);
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if (st.ffAmux) {
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SigSpec Y = st.ffAmux->getPort("\\Y");
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SigSpec AB = st.ffAmux->getPort(st.ffAcepol ? "\\B" : "\\A");
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SigSpec S = st.ffAmux->getPort("\\S");
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if (rstmux) {
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SigSpec Y = rstmux->getPort("\\Y");
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SigSpec AB = rstmux->getPort(rstpol ? "\\A" : "\\B");
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SigSpec S = rstmux->getPort("\\S");
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A.replace(Y, AB);
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cell->setPort("\\CEA2", st.ffAcepol ? S : pm.module->Not(NEW_ID, S));
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cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEA2", State::S1);
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cell->setPort("\\A", A);
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cell->setPort(rstport, State::S0);
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if (cemux) {
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SigSpec Y = cemux->getPort("\\Y");
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SigSpec BA = cemux->getPort(cepol ? "\\B" : "\\A");
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SigSpec S = cemux->getPort("\\S");
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A.replace(Y, BA);
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cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort(ceport, State::S1);
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cell->setPort(port, A);
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};
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if (st.ffA) {
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f("\\A", st.ffA, st.ffAcemux, st.ffAcepol, "\\CEA2", st.ffArstmux, st.ffArstpol, "\\RSTA");
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cell->setParam("\\AREG", 1);
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}
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if (st.ffB) {
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SigSpec B = cell->getPort("\\B");
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SigSpec D = st.ffB->getPort("\\D");
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SigSpec Q = st.ffB->getPort("\\Q");
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B.replace(Q, D);
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if (st.ffBmux) {
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SigSpec Y = st.ffBmux->getPort("\\Y");
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SigSpec AB = st.ffBmux->getPort(st.ffBcepol ? "\\B" : "\\A");
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SigSpec S = st.ffBmux->getPort("\\S");
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B.replace(Y, AB);
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cell->setPort("\\CEB2", st.ffBcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEB2", State::S1);
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cell->setPort("\\B", B);
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f("\\B", st.ffB, st.ffBcemux, st.ffBcepol, "\\CEB2", st.ffBrstmux, st.ffBrstpol, "\\RSTB");
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cell->setParam("\\BREG", 1);
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}
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if (st.ffC) {
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SigSpec C = cell->getPort("\\C");
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SigSpec D = st.ffC->getPort("\\D");
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SigSpec Q = st.ffC->getPort("\\Q");
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C.replace(Q, D);
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if (st.ffCmux) {
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SigSpec Y = st.ffCmux->getPort("\\Y");
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SigSpec AB = st.ffCmux->getPort(st.ffCcepol ? "\\B" : "\\A");
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SigSpec S = st.ffCmux->getPort("\\S");
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C.replace(Y, AB);
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cell->setPort("\\CEC", st.ffCcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEC", State::S1);
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cell->setPort("\\C", C);
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f("\\C", st.ffC, st.ffCcemux, st.ffCcepol, "\\CEC", st.ffCrstmux, st.ffCrstpol, "\\RSTC");
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cell->setParam("\\CREG", 1);
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}
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if (st.ffD) {
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SigSpec D_ = cell->getPort("\\D");
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SigSpec D = st.ffD->getPort("\\D");
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SigSpec Q = st.ffD->getPort("\\Q");
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D_.replace(Q, D);
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if (st.ffDmux) {
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SigSpec Y = st.ffDmux->getPort("\\Y");
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SigSpec AB = st.ffDmux->getPort(st.ffDcepol ? "\\B" : "\\A");
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SigSpec S = st.ffDmux->getPort("\\S");
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D_.replace(Y, AB);
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cell->setPort("\\CED", st.ffDcepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CED", State::S1);
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cell->setPort("\\D", D_);
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f("\\D", st.ffD, st.ffDcemux, st.ffDcepol, "\\CED", st.ffDrstmux, st.ffDrstpol, "\\RSTD");
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cell->setParam("\\DREG", 1);
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}
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if (st.ffM) {
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@ -516,9 +473,9 @@ struct XilinxDspPass : public Pass {
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log("\n");
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log(" xilinx_dsp [options] [selection]\n");
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log("\n");
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log("Pack input registers (A, B, C, D, AD; with optional enable), pipeline registers\n");
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log("(M; with optional enable), output registers (P; with optional enable),\n");
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log("pre-adder and/or post-adder into Xilinx DSP resources.\n");
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log("Pack input registers (A, B, C, D, AD; with optional enable/reset), pipeline\n");
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log("registers (M; with optional enable/reset), output registers (P; with optional\n");
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log("enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.\n");
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log("\n");
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log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
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log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
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@ -528,8 +485,6 @@ struct XilinxDspPass : public Pass {
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log("where 'P' is right-shifted by 18-bits and used as an input to the post-adder (a\n");
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log("pattern common for summing partial products to implement wide multiplies).\n");
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log("\n");
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log("Not currently supported: reset (RST*) inputs on any register.\n");
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log("\n");
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log("\n");
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log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
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log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n");
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@ -2,12 +2,13 @@ pattern xilinx_dsp
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state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffMrstpol ffPcepol ffPrstpol
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state <int> ffPoffset
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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state <Cell*> ffAD ffADcemux ffADrstmux ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffC ffCcemux ffCrstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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@ -54,7 +55,7 @@ code unextend sigA sigB sigC sigD sigM
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sigM = P;
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endcode
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code argQ ffAD ffADmux ffADcepol sigA clock
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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@ -62,8 +63,10 @@ code argQ ffAD ffADmux ffADcepol sigA clock
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ffAD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffADmux = dffcemux;
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ffADcemux = dffcemux;
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ffADrstmux = dffrstmux;
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ffADcepol = dffcepol;
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ffADrstpol = dffrstpol;
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}
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sigA = dffD;
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}
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@ -100,7 +103,7 @@ code sigA sigD
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}
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endcode
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code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol
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// Only search for ffA if there was a pre-adder
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// (otherwise ffA would have been matched as ffAD)
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if (preAdd) {
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@ -111,8 +114,10 @@ code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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ffA = dff;
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clock = dffclock;
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if (dffcemux) {
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ffAmux = dffcemux;
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ffAcemux = dffcemux;
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ffArstmux = dffrstmux;
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ffAcepol = dffcepol;
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ffArstpol = dffrstpol;
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}
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sigA = dffD;
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}
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@ -121,14 +126,16 @@ code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA && !ffAmux);
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log_assert(!ffA && !ffAcemux && !ffArstmux);
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std::swap(ffA, ffAD);
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std::swap(ffAmux, ffADmux);
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std::swap(ffAcemux, ffADcemux);
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std::swap(ffArstmux, ffADrstmux);
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ffAcepol = ffADcepol;
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ffArstpol = ffADrstpol;
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}
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endcode
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code argQ ffB ffBmux ffBcepol sigB clock
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code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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@ -136,15 +143,17 @@ code argQ ffB ffBmux ffBcepol sigB clock
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ffB = dff;
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clock = dffclock;
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if (dffcemux) {
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ffBmux = dffcemux;
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ffBcemux = dffcemux;
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ffBrstmux = dffrstmux;
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ffBcepol = dffcepol;
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ffBrstpol = dffrstpol;
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}
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sigB = dffD;
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}
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}
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endcode
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code argQ ffD ffDmux ffDcepol sigD clock
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code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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@ -152,8 +161,10 @@ code argQ ffD ffDmux ffDcepol sigD clock
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ffD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffDmux = dffcemux;
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ffDcemux = dffcemux;
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ffDrstmux = dffrstmux;
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ffDcepol = dffcepol;
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ffDrstpol = dffrstpol;
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}
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sigD = dffD;
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}
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@ -255,16 +266,18 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCmux ffCcepol sigC clock
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if (param(dsp, \CREG).as_int() == 0) {
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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if (param(dsp, \CREG).as_int() == 0 && sigC != sigP) {
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffcemux) {
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ffCmux = dffcemux;
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ffCcemux = dffcemux;
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ffCrstmux = dffrstmux;
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ffCcepol = dffcepol;
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ffCrstpol = dffrstpol;
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}
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sigC = dffD;
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}
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@ -278,67 +291,102 @@ endcode
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// #######################
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subpattern in_dffe
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arg argQ clock ffcepol
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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filter GetSize(port(ff, \Q)) >= GetSize(argQ)
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slice offset GetSize(port(ff, \Q))
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filter offset+GetSize(argQ) <= GetSize(port(ff, \Q))
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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SigSpec Q = port(ff, \Q);
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if (ffoffset + GetSize(argQ) > GetSize(Q))
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reject;
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for (int i = 1; i < GetSize(argQ); i++)
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if (Q[ffoffset+i] != argQ[i])
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reject;
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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|
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match ffrstmux
|
||||
if !argD.empty()
|
||||
select ffrstmux->type.in($mux)
|
||||
index <SigSpec> port(ffrstmux, \Y) === argD
|
||||
|
||||
choice <IdString> BA {\B, \A}
|
||||
// DSP48E1 only supports reset to zero
|
||||
select port(ffrstmux, BA).is_fully_zero()
|
||||
|
||||
define <bool> pol (BA == \B)
|
||||
set ffrstpol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argQ
|
||||
if (ff) {
|
||||
for (auto c : argQ.chunks())
|
||||
if (c.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
code argD
|
||||
if (ffrstmux) {
|
||||
dffrstmux = ffrstmux;
|
||||
dffrstpol = ffrstpol;
|
||||
argD = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
dffD.replace(port(ffrstmux, \Y), argD);
|
||||
|
||||
if (clock != SigBit()) {
|
||||
if (port(ff, \CLK) != clock)
|
||||
reject;
|
||||
}
|
||||
dffclock = port(ff, \CLK);
|
||||
|
||||
dff = ff;
|
||||
dffD = argQ;
|
||||
dffD.replace(port(ff, \Q), port(ff, \D));
|
||||
// Only search for ffcemux if argQ has at
|
||||
// least 3 users (ff, <upstream>, ffcemux) and
|
||||
// its ff.D only has two (ff, ffcemux)
|
||||
// Only search for ffrstmux if argQ has at
|
||||
// least 3 users (ff, <upstream>, ffrstmux) and
|
||||
// dffD only has two (ff, ffrstmux)
|
||||
if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
|
||||
argQ = SigSpec();
|
||||
}
|
||||
else {
|
||||
dff = nullptr;
|
||||
argQ = SigSpec();
|
||||
argD = SigSpec();
|
||||
}
|
||||
else
|
||||
dffrstmux = nullptr;
|
||||
endcode
|
||||
|
||||
match ffcemux
|
||||
if !argQ.empty()
|
||||
if !argD.empty()
|
||||
select ffcemux->type.in($mux)
|
||||
index <SigSpec> port(ffcemux, \Y) === port(ff, \D)
|
||||
filter GetSize(port(ffcemux, \Y)) >= GetSize(dffD)
|
||||
slice offset GetSize(port(ffcemux, \Y))
|
||||
filter offset+GetSize(dffD) <= GetSize(port(ffcemux, \Y))
|
||||
filter port(ffcemux, \Y).extract(offset, GetSize(dffD)) == dffD
|
||||
index <SigSpec> port(ffcemux, \Y) === argD
|
||||
choice <IdString> AB {\A, \B}
|
||||
filter offset+GetSize(argQ) <= GetSize(port(ffcemux, \Y))
|
||||
filter port(ffcemux, AB).extract(offset, GetSize(argQ)) == argQ
|
||||
index <SigSpec> port(ffcemux, AB) === argQ
|
||||
define <bool> pol (AB == \A)
|
||||
set ffcepol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code
|
||||
code argD
|
||||
if (ffcemux) {
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
dffD = port(ffcemux, dffcepol ? \B : \A);
|
||||
dffD.replace(port(ffcemux, \Y), argD);
|
||||
}
|
||||
else
|
||||
dffcemux = nullptr;
|
||||
|
|
@ -379,7 +427,6 @@ code argD argQ
|
|||
SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
|
||||
if (ffoffset + GetSize(argD) > GetSize(BA))
|
||||
reject;
|
||||
|
||||
for (int i = 1; i < GetSize(argD); i++)
|
||||
if (BA[ffoffset+i] != argD[i])
|
||||
reject;
|
||||
|
|
@ -440,7 +487,7 @@ match ff
|
|||
select param(ff, \CLK_POLARITY).as_bool()
|
||||
|
||||
slice offset GetSize(port(ff, \D))
|
||||
index <SigSpec> port(ff, \D)[offset] === argD[0]
|
||||
index <SigBit> port(ff, \D)[offset] === argD[0]
|
||||
|
||||
filter (!ffcemux && !ffrstmux) || ffoffset == offset
|
||||
set ffoffset offset
|
||||
|
|
|
|||
Loading…
Reference in New Issue