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Cleanup xilinx_dsp
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@ -2,7 +2,7 @@ pattern xilinx_dsp_pack
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
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