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pmgen to also iterate over all module ports

This commit is contained in:
Eddie Hung 2019-08-22 11:15:16 -07:00
parent 74bd190d3b
commit 9f3ed1726e
1 changed files with 4 additions and 2 deletions
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6
passes/pmgen/pmgen.py
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@ -390,8 +390,6 @@ with open(outfile, "w") as f:
print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
print(" for (auto bit : sigmap(sig)) {", file=f)
print(" if (bit.wire == nullptr) continue;", file=f)
print(" if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f)
print(" sigusers[bit].insert(nullptr);", file=f)
print(" sigusers[bit].insert(cell);", file=f)
print(" }", file=f)
print(" }", file=f)
@ -450,6 +448,10 @@ with open(outfile, "w") as f:
print(" for (auto &conn : cell->connections())", file=f)
print(" add_siguser(conn.second, cell);", file=f)
print(" }", file=f)
print(" for (auto port : module->ports)", file=f)
print(" add_siguser(module->wire(port), nullptr);", file=f)
print(" ", file=f)
print(" for (auto cell : cells) {", file=f)
for index in range(len(blocks)):