mirror of https://github.com/YosysHQ/yosys.git
Remove output_bits
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231ddbf95c
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@ -214,19 +214,8 @@ struct XilinxSrlPass : public Pass {
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pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
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pm.run_fixed(run_fixed);
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}
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if (variable) {
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// Since `nusers` does not count module ports as a user,
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// and since `sigmap` does not always make such ports
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// the canonical signal.. need to maintain a pool these
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// ourselves
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for (auto p : module->ports) {
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auto w = module->wire(p);
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if (w->port_output)
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for (auto b : pm.sigmap(w))
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pm.ud_variable.output_bits.insert(b);
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}
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if (variable)
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pm.run_variable(run_variable);
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}
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}
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}
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} XilinxSrlPass;
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@ -152,13 +152,12 @@ pattern variable
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state <int> shiftx_width
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udata <int> minlen
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udata <pool<SigBit>> output_bits
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udata <vector<Cell*>> chain
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match shiftx
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select shiftx->type.in($shiftx)
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select !shiftx->has_keep_attr()
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select param(shiftx, \Y_WIDTH) == 1
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select param(shiftx, \Y_WIDTH).as_int() == 1
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filter param(shiftx, \A_WIDTH).as_int() >= minlen
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endmatch
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@ -170,7 +169,6 @@ match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)
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select nusers(port(first, \Q)) == 2
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index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1]
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filter !output_bits.count(port(first, \Q))
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endmatch
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code
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@ -194,7 +192,6 @@ match next
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select !next->has_keep_attr()
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 3
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filter !output_bits.count(port(next, \Q))
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index <IdString> next->type === chain.back()->type
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index <SigBit> port(next, \Q) === port(chain.back(), \D)
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index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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@ -202,6 +199,11 @@ endmatch
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code
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if (next) {
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auto sig = port(next, \Q);
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log_warning("nusers of '%s'\n", log_signal(sig));
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for (auto bit : sigmap(sig))
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for (auto user : sigusers[bit])
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log_warning("\t%s\n", log_id(user));
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chain.push_back(next);
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if (GetSize(chain) < shiftx_width)
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subpattern(tail);
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