mirror of https://github.com/YosysHQ/yosys.git
Do not perform width-checks for DSP48E1 which is much more complicated
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@ -278,17 +278,6 @@ endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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// TODO for DSP48E1, which will have sign extended inputs/outputs
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//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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//int actual_mul_width = GetSize(sigP);
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//int actual_acc_width = GetSize(sigC);
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//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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// reject;
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
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// reject;
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sigP = port(postAdd, \Y);
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}
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endcode
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