mirror of https://github.com/YosysHQ/yosys.git
Add initial USE_SIMD=FOUR12 support
This commit is contained in:
Eddie Hung
parent
2c04430445
commit
5a6552e56b
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@ -25,6 +25,161 @@ PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
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{
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std::deque<Cell*> simd12, simd24;
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for (auto cell : selected_cells) {
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if (!cell->type.in("$add"))
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continue;
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SigSpec Y = cell->getPort("\\Y");
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if (!Y.is_chunk())
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continue;
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if (!Y.as_chunk().wire->get_strpool_attribute("\\use_dsp").count("simd"))
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continue;
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if (GetSize(Y) > 25)
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continue;
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SigSpec A = cell->getPort("\\A");
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SigSpec B = cell->getPort("\\B");
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if (GetSize(Y) <= 13) {
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if (GetSize(A) > 12)
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continue;
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if (GetSize(B) > 12)
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continue;
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simd12.push_back(cell);
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}
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else {
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if (GetSize(A) > 24)
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continue;
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if (GetSize(B) > 24)
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continue;
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simd24.push_back(cell);
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}
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}
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auto addDsp = [module] {
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Cell *cell = module->addCell(NEW_ID, "\\DSP48E1");
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cell->setParam("\\ACASCREG", 0);
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cell->setParam("\\ADREG", 0);
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cell->setParam("\\A_INPUT", Const("DIRECT"));
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cell->setParam("\\ALUMODEREG", 0);
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cell->setParam("\\AREG", 0);
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cell->setParam("\\BCASCREG", 0);
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cell->setParam("\\B_INPUT", Const("DIRECT"));
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cell->setParam("\\BREG", 0);
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cell->setParam("\\CARRYINREG", 0);
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cell->setParam("\\CARRYINSELREG", 0);
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cell->setParam("\\CREG", 0);
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cell->setParam("\\DREG", 0);
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cell->setParam("\\INMODEREG", 0);
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cell->setParam("\\MREG", 0);
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cell->setParam("\\OPMODEREG", 0);
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cell->setParam("\\PREG", 0);
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cell->setParam("\\USE_MULT", Const("NONE"));
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cell->setPort("\\D", Const(0, 24));
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cell->setPort("\\INMODE", Const(0, 5));
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cell->setPort("\\ALUMODE", Const(0, 4));
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cell->setPort("\\OPMODE", Const(0, 7));
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cell->setPort("\\CARRYINSEL", Const(0, 3));
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cell->setPort("\\ACIN", Const(0, 30));
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cell->setPort("\\BCIN", Const(0, 18));
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cell->setPort("\\PCIN", Const(0, 48));
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cell->setPort("\\CARRYIN", Const(0, 1));
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return cell;
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};
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SigSpec AB;
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SigSpec C;
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SigSpec P;
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SigSpec CARRYOUT;
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auto f12 = [&AB,&C,&P,&CARRYOUT,module](Cell *lane) {
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SigSpec A = lane->getPort("\\A");
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SigSpec B = lane->getPort("\\B");
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SigSpec Y = lane->getPort("\\Y");
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A.extend_u0(12, lane->getParam("\\A_SIGNED").as_bool());
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B.extend_u0(12, lane->getParam("\\B_SIGNED").as_bool());
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AB.append(A);
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C.append(B);
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if (GetSize(Y) < 13)
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Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
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else
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log_assert(GetSize(Y) == 13);
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P.append(Y.extract(0, 12));
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CARRYOUT.append(Y[12]);
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};
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while (simd12.size() > 1) {
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AB = SigSpec();
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C = SigSpec();
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P = SigSpec();
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CARRYOUT = SigSpec();
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Cell *lane1 = simd12.front();
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simd12.pop_front();
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Cell *lane2 = simd12.front();
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simd12.pop_front();
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Cell *lane3 = nullptr;
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Cell *lane4 = nullptr;
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if (!simd12.empty()) {
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lane3 = simd12.front();
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simd12.pop_front();
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if (!simd12.empty()) {
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lane4 = simd12.front();
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simd12.pop_front();
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}
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}
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log("Analysing %s.%s for Xilinx DSP SIMD12 packing.\n", log_id(module), log_id(lane1));
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Cell *cell = addDsp();
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cell->setParam("\\USE_SIMD", Const("FOUR12"));
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// X = A:B
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// Y = 0
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// Z = C
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cell->setPort("\\OPMODE", Const::from_string("0110011"));
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log_assert(lane1);
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log_assert(lane2);
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f12(lane1);
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f12(lane2);
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if (lane3) {
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f12(lane3);
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if (lane4)
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f12(lane4);
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else {
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AB.append(Const(0, 12));
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C.append(Const(0, 12));
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P.append(module->addWire(NEW_ID, 12));
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CARRYOUT.append(module->addWire(NEW_ID, 1));
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}
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}
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else {
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AB.append(Const(0, 24));
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C.append(Const(0, 24));
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P.append(module->addWire(NEW_ID, 24));
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CARRYOUT.append(module->addWire(NEW_ID, 2));
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}
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log_assert(GetSize(AB) == 48);
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log_assert(GetSize(C) == 48);
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log_assert(GetSize(P) == 48);
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log_assert(GetSize(CARRYOUT) == 4);
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cell->setPort("\\A", AB.extract(18, 30));
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cell->setPort("\\B", AB.extract(0, 18));
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cell->setPort("\\C", C);
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cell->setPort("\\P", P);
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cell->setPort("\\CARRYOUT", CARRYOUT);
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module->remove(lane1);
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module->remove(lane2);
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if (lane3) module->remove(lane3);
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if (lane4) module->remove(lane4);
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module->design->select(module, cell);
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}
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}
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void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp;
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@ -281,6 +436,8 @@ struct XilinxDspPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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pack_xilinx_simd(module, module->selected_cells());
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xilinx_dsp_pm pm(module, module->selected_cells());
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dict<SigBit, Cell*> bit_to_driver;
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auto f = [&bit_to_driver](xilinx_dsp_pm &pm){ pack_xilinx_dsp(bit_to_driver, pm); };
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