mirror of https://github.com/YosysHQ/yosys.git
Pack CREG
This commit is contained in:
Eddie Hung
parent
6a9205280f
commit
74a5c802f7
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@ -38,6 +38,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("ffBmux: %s\n", log_id(st.ffBmux, "--"));
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log("ffC: %s\n", log_id(st.ffC, "--"));
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log("ffCmux: %s\n", log_id(st.ffCmux, "--"));
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log("ffD: %s\n", log_id(st.ffD, "--"));
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log("ffDmux: %s\n", log_id(st.ffDmux, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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@ -53,7 +55,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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Cell *cell = st.dsp;
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bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
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SigSpec C = st.sigC;
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SigSpec P = st.sigP;
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if (st.preAdd) {
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@ -91,15 +92,21 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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opmode[4] = st.postAddMux->getPort("\\S");
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pm.autoremove(st.postAddMux);
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}
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else if (st.ffP && C == P) {
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C = SigSpec();
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else if (st.ffP && st.sigC == P)
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opmode[4] = State::S0;
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}
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else
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opmode[4] = State::S1;
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opmode[6] = State::S0;
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opmode[5] = State::S1;
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if (opmode[4] != State::S0) {
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if (st.postAddMuxAB == "\\A")
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st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
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else
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st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
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cell->setPort("\\C", st.sigC);
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}
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pm.autoremove(st.postAdd);
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}
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@ -143,10 +150,30 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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cell->setParam("\\BREG", 1);
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}
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if (st.ffC) {
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SigSpec C = cell->getPort("\\C");
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SigSpec D = st.ffC->getPort("\\D");
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SigSpec Q = st.ffC->getPort("\\Q");
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C.replace(Q, D);
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if (st.ffCmux) {
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SigSpec Y = st.ffCmux->getPort("\\Y");
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SigSpec AB = st.ffCmux->getPort(st.ffCenpol ? "\\B" : "\\A");
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SigSpec S = st.ffCmux->getPort("\\S");
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C.replace(Y, AB);
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cell->setPort("\\CEC", st.ffCenpol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\CEC", State::S1);
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cell->setPort("\\C", C);
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cell->setParam("\\CREG", 1);
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}
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if (st.ffD) {
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SigSpec D_ = cell->getPort("\\D");
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SigSpec D = st.ffB->getPort("\\D");
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SigSpec Q = st.ffB->getPort("\\Q");
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SigSpec D = st.ffD->getPort("\\D");
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SigSpec Q = st.ffD->getPort("\\Q");
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D_.replace(Q, D);
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if (st.ffDmux) {
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@ -205,6 +232,12 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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if (st.ffC)
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log(" ffC:%s", log_id(st.ffC));
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if (st.ffD)
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log(" ffD:%s", log_id(st.ffD));
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if (st.ffM)
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log(" ffM:%s", log_id(st.ffM));
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@ -214,12 +247,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("\n");
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}
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if (!C.empty()) {
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if (GetSize(C) < 48)
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C.extend_u0(48, true);
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cell->setPort("\\C", C);
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}
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if (GetSize(P) < 48)
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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cell->setPort("\\P", P);
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@ -265,6 +292,8 @@ struct XilinxDspPass : public Pass {
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for (auto cell : module->cells()) {
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if (cell->type != "\\DSP48E1")
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continue;
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if (cell->parameters.at("\\CREG", State::S1).as_bool())
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continue;
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SigSpec &opmode = cell->connections_.at("\\OPMODE");
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if (opmode.extract(4,3) != Const::from_string("011"))
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continue;
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@ -1,29 +1,29 @@
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pattern xilinx_dsp
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state <std::function<SigSpec(const SigSpec&, bool)>> unextend
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state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigD sigffDmuxY sigM sigP
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAenpol ffADenpol ffBenpol ffDenpol ffMenpol ffPenpol
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state <bool> ffAenpol ffADenpol ffBenpol ffCenpol ffDenpol ffMenpol ffPenpol
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state <int> ffPoffset
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code unextend sigA sigffAmuxY sigB sigffBmuxY sigC sigD sigffDmuxY sigM
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unextend = [](const SigSpec &sig, bool keep_sign) {
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code unextend sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (!keep_sign && sig[i].wire)
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(dsp, \A), false);
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sigB = unextend(port(dsp, \B), false);
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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sigC = dsp->connections_.at(\C, SigSpec());
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sigD = dsp->connections_.at(\D, SigSpec());
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@ -42,6 +42,7 @@ code unextend sigA sigffAmuxY sigB sigffBmuxY sigC sigD sigffDmuxY sigM
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sigffAmuxY = SigSpec();
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sigffBmuxY = SigSpec();
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sigffCmuxY = SigSpec();
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sigffDmuxY = SigSpec();
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endcode
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@ -260,9 +261,9 @@ code sigD sigffDmuxY clock
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SigSpec D = sigD;
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D.replace(port(ffD, \Q), port(ffD, \D));
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// Only search for ffBmux if ffB.Q has at
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// least 3 users (ffB, dsp, ffBmux) and
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// its ffB.D only has two (ffB, ffBmux)
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// Only search for ffDmux if ffD.Q has at
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// least 3 users (ffD, dsp, ffDmux) and
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// its ffD.D only has two (ffD, ffDmux)
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if (nusers(sigD) >= 3 && nusers(D) == 2)
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sigffDmuxY = sigD;
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sigD = std::move(D);
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@ -276,7 +277,7 @@ match ffDmux
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filter GetSize(port(ffDmux, \Y)) >= GetSize(sigD)
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slice offset GetSize(port(ffDmux, \Y))
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filter offset+GetSize(sigD) <= GetSize(port(ffDmux, \Y))
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filter port(ffDmux, \Y).extract(offset, GetSize(sigB)) == sigD
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filter port(ffDmux, \Y).extract(offset, GetSize(sigD)) == sigD
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffDmuxY) <= GetSize(port(ffDmux, \Y))
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filter port(ffDmux, AB).extract(offset, GetSize(sigffDmuxY)) == sigffDmuxY
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@ -290,17 +291,17 @@ match ffMmux
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if nusers(sigM) == 2
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select ffMmux->type.in($mux)
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choice <IdString> BA {\B, \A}
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// new-value net must have exactly two users: dsp and ffM
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// new-value net must have exactly two users: dsp and ffMmux
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select nusers(port(ffMmux, BA)) == 2
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have at least three users: ffMmux, ffM, downstream sink(s)
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select nusers(port(ffMmux, AB)) >= 3
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// ffMmux output must have two users: ffMmux and ffM.D
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select nusers(port(ffMmux, \Y)) == 2
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filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM)
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filter port(ffMmux, BA) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
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filter GetSize(unextend(port(ffMmux, BA))) <= GetSize(sigM)
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filter unextend(port(ffMmux, BA)) == sigM.extract(0, GetSize(unextend(port(ffMmux, BA))))
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// Remaining bits on sigM must not have any other users
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filter nusers(sigM.extract_end(GetSize(port(ffMmux, BA)))) <= 1
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filter nusers(sigM.extract_end(GetSize(unextend(port(ffMmux, BA))))) <= 1
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define <bool> pol (AB == \A)
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set ffMenpol pol
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optional
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@ -367,9 +368,9 @@ match postAdd
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select nusers(port(postAdd, AB)) <= 3
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filter ffMmux || nusers(port(postAdd, AB)) == 2
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filter !ffMmux || nusers(port(postAdd, AB)) == 3
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filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
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filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
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filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
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filter GetSize(unextend(port(postAdd, AB))) <= GetSize(sigP)
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filter unextend(port(postAdd, AB)) == sigP.extract(0, GetSize(unextend(port(postAdd, AB))))
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filter nusers(sigP.extract_end(GetSize(unextend(port(postAdd, AB))))) <= 1
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set postAddAB AB
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optional
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endmatch
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@ -495,6 +496,56 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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match ffC
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if param(dsp, \CREG).as_int() == 0
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select ffC->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffC, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffC, \Q)) >= GetSize(sigD)
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slice offset GetSize(port(ffC, \Q))
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filter offset+GetSize(sigC) <= GetSize(port(ffC, \Q))
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filter port(ffC, \Q).extract(offset, GetSize(sigC)) == sigC
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optional
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endmatch
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code sigC sigffCmuxY clock
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if (ffC) {
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for (auto b : port(ffC, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffC, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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SigSpec C = sigC;
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C.replace(port(ffC, \Q), port(ffC, \D));
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// Only search for ffCmux if ffC.Q has at
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// least 3 users (ffC, dsp, ffCmux) and
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// its ffC.D only has two (ffC, ffCmux)
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if (nusers(sigC) >= 3 && nusers(C) == 2)
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sigffCmuxY = sigC;
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sigC = std::move(C);
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}
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endcode
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match ffCmux
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if !sigffCmuxY.empty()
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select ffCmux->type.in($mux)
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index <SigSpec> port(ffCmux, \Y) === port(ffC, \D)
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filter GetSize(port(ffCmux, \Y)) >= GetSize(sigC)
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slice offset GetSize(port(ffCmux, \Y))
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filter offset+GetSize(sigC) <= GetSize(port(ffCmux, \Y))
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filter port(ffCmux, \Y).extract(offset, GetSize(sigC)) == sigC
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffCmuxY) <= GetSize(port(ffCmux, \Y))
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filter port(ffCmux, AB).extract(offset, GetSize(sigffCmuxY)) == sigffCmuxY
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define <bool> pol (AB == \A)
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set ffCenpol pol
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optional
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endmatch
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code
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accept;
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endcode
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