riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Another oops

This commit is contained in:
Eddie Hung 2019-08-30 15:02:53 -07:00
parent 44a35015b3
commit c497114e94
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/pmgen/xilinx_dsp.cc
View File

@ -101,7 +101,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
SigSpec Q = st.ffM->getPort("\\Q");
P.replace(pm.sigmap(D), Q);
cell->setParam("\\MREG", State::S1);
if (st.ffP->type == "$dff")
if (st.ffM->type == "$dff")
cell->setPort("\\CEM", State::S1);
//else if (st.ffP->type == "$dffe")
// cell->setPort("\\CEM", st.ffM->getPort("\\EN"));