mirror of https://github.com/YosysHQ/yosys.git
Make unextend a udata
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@ -1,6 +1,6 @@
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pattern xilinx_dsp
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state <std::function<SigSpec(const SigSpec&)>> unextend
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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@ -23,7 +23,7 @@ match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code unextend sigA sigB sigC sigD sigM
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code sigA sigB sigC sigD sigM
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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@ -396,7 +396,6 @@ endcode
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subpattern out_dffe
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arg argD argQ clock
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arg unextend
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code
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dff = nullptr;
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