mirror of https://github.com/YosysHQ/yosys.git
Same for variable length
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@ -181,7 +181,7 @@ endcode
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pattern variable
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state <IdString> clk_port
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state <IdString> clk_port en_port
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state <int> shiftx_width
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state <int> slice
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udata <int> minlen
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@ -207,12 +207,18 @@ match first
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set slice idx
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endmatch
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code clk_port
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code clk_port en_port
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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clk_port = \C;
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else if (first->type.in($dff, $dffe))
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clk_port = \CLK;
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else log_abort();
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if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
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en_port = \E;
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else if (first->type.in($dff, $dffe))
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en_port = \EN;
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else log_abort();
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chain.emplace_back(first, slice);
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subpattern(tail);
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finally
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@ -229,6 +235,7 @@ arg shiftx
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arg shiftx_width
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arg slice
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arg clk_port
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arg en_port
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match next
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semioptional
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@ -241,6 +248,7 @@ match next
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index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
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index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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filter port(next, clk_port) == port(first, clk_port)
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filter en_port == IdString() || port(next, en_port) == port(first, en_port)
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set slice idx
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endmatch
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