mirror of https://github.com/YosysHQ/yosys.git
Add HOLD/RST support for SB_MAC16
This commit is contained in:
Eddie Hung
parent
2766465a2b
commit
429c9852ce
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@ -33,13 +33,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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log("\n");
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log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
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log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
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log("ffCD: %s %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"), log_id(st.ffCDrstmux, "--"));
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log("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--"));
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log("ffH: %s n/a %s\n", log_id(st.ffH, "--"), log_id(st.ffHrstmux, "--"));
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log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
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log("ffH: %s\n", log_id(st.ffH, "--"));
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log("add: %s\n", log_id(st.add, "--"));
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log("mux: %s\n", log_id(st.mux, "--"));
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log("ffO: %s\n", log_id(st.ffO, "--"));
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log("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOcemux, "--"), log_id(st.ffOrstmux, "--"));
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#endif
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log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
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@ -98,13 +98,35 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setParam("\\C_REG", st.ffCD ? State::S1 : State::S0);
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cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
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cell->setPort("\\AHOLD", State::S0);
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cell->setPort("\\BHOLD", State::S0);
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cell->setPort("\\CHOLD", State::S0);
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cell->setPort("\\DHOLD", State::S0);
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SigSpec AHOLD, BHOLD, CDHOLD;
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if (st.ffAcemux)
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AHOLD = st.ffAcepol ? pm.module->Not(NEW_ID, st.ffAcemux->getPort("\\S")) : st.ffAcemux->getPort("\\S");
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else
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AHOLD = State::S0;
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if (st.ffBcemux)
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BHOLD = st.ffBcepol ? pm.module->Not(NEW_ID, st.ffBcemux->getPort("\\S")) : st.ffBcemux->getPort("\\S");
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else
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BHOLD = State::S0;
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if (st.ffCDcemux)
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CDHOLD = st.ffCDcepol ? pm.module->Not(NEW_ID, st.ffCDcemux->getPort("\\S")) : st.ffCDcemux->getPort("\\S");
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else
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CDHOLD = State::S0;
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cell->setPort("\\AHOLD", AHOLD);
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cell->setPort("\\BHOLD", BHOLD);
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cell->setPort("\\CHOLD", CDHOLD);
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cell->setPort("\\DHOLD", CDHOLD);
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cell->setPort("\\IRSTTOP", State::S0);
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cell->setPort("\\IRSTBOT", State::S0);
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SigSpec IRSTTOP, IRSTBOT;
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if (st.ffArstmux)
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IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffArstmux->getPort("\\S"));
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else
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IRSTTOP = State::S0;
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if (st.ffBrstmux)
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IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBrstmux->getPort("\\S"));
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else
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IRSTBOT = State::S0;
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cell->setPort("\\IRSTTOP", IRSTTOP);
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cell->setPort("\\IRSTBOT", IRSTBOT);
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if (st.clock != SigBit())
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{
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@ -187,11 +209,21 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setPort("\\ADDSUBBOT", State::S0);
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}
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cell->setPort("\\ORSTTOP", State::S0);
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cell->setPort("\\ORSTBOT", State::S0);
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SigSpec OHOLD;
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if (st.ffOcemux)
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OHOLD = st.ffOcemux ? pm.module->Not(NEW_ID, st.ffOcemux->getPort("\\S")) : st.ffOcemux->getPort("\\S");
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else
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OHOLD = State::S0;
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cell->setPort("\\OHOLDTOP", OHOLD);
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cell->setPort("\\OHOLDBOT", OHOLD);
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cell->setPort("\\OHOLDTOP", State::S0);
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cell->setPort("\\OHOLDBOT", State::S0);
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SigSpec ORST;
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if (st.ffOrstmux)
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ORST = st.ffOrstmux ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
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else
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ORST = State::S0;
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cell->setPort("\\ORSTTOP", ORST);
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cell->setPort("\\ORSTBOT", ORST);
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SigSpec acc_reset = State::S0;
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if (st.mux) {
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@ -200,7 +232,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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else
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acc_reset = pm.module->Not(NEW_ID, st.mux->getPort("\\S"));
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}
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cell->setPort("\\OLOADTOP", acc_reset);
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cell->setPort("\\OLOADBOT", acc_reset);
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@ -9,8 +9,8 @@ state <IdString> addAB muxAB
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state <bool> ffAcepol ffBcepol ffCDcepol ffOcepol
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state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
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state <Cell*> ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux ffCDrstmux
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state <Cell*> ffFJKG ffFJKGrstmux ffH ffHrstmux ffO ffOcemux ffOrstmux
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state <Cell*> ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux
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state <Cell*> ffFJKG ffH ffO ffOcemux ffOrstmux
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// subpattern
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state <SigSpec> argQ argD
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@ -105,75 +105,79 @@ code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol
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}
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endcode
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code argD ffFJKG ffFJKGrstmux sigH sigO clock clock_pol
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code argD ffFJKG sigH sigO clock clock_pol
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if (nusers(sigH) == 2 &&
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(mul->type != \SB_MAC16 ||
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(!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
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argD = sigH;
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subpattern(out_dffe);
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if (dff) {
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ffFJKG = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux)
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ffFJKGrstmux = dffrstmux;
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// F/J/K/G do not have a CE-like (hold) input
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if (dffcemux)
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reject;
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goto reject_ffFJKG;
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// Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
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// shared with A and B
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if ((ffArstmux != NULL) != (ffFJKGrstmux != NULL))
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reject;
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if ((ffBrstmux != NULL) != (ffFJKGrstmux != NULL))
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reject;
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if ((ffArstmux != NULL) != (dffrstmux != NULL))
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goto reject_ffFJKG;
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if ((ffBrstmux != NULL) != (dffrstmux != NULL))
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goto reject_ffFJKG;
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if (ffArstmux) {
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if (port(ffArstmux, \S) != port(ffFJKGrstmux, \S))
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reject;
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if (port(ffArstmux, \S) != port(dffrstmux, \S))
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goto reject_ffFJKG;
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if (ffArstpol != dffrstpol)
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reject;
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goto reject_ffFJKG;
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}
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if (ffBrstmux) {
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if (port(ffBrstmux, \S) != port(ffFJKGrstmux, \S))
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reject;
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if (port(ffBrstmux, \S) != port(dffrstmux, \S))
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goto reject_ffFJKG;
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if (ffBrstpol != dffrstpol)
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reject;
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goto reject_ffFJKG;
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}
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ffFJKG = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigH = dffQ;
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}
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}
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if (0) {
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reject_ffFJKG: ;
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}
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endcode
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code argD ffH ffHrstmux sigH sigO clock clock_pol
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if (nusers(sigH) == 2 &&
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code argD ffH sigH sigO clock clock_pol
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if (ffFJKG && nusers(sigH) == 2 &&
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(mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
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argD = sigH;
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subpattern(out_dffe);
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if (dff) {
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// H does not have a CE-like (hold) input
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if (dffcemux)
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goto reject_ffH;
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// Reset signal of H (IRSTBOT) shared with B
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if ((ffBrstmux != NULL) != (dffrstmux != NULL))
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goto reject_ffH;
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if (ffBrstmux) {
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if (port(ffBrstmux, \S) != port(dffrstmux, \S))
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goto reject_ffH;
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if (ffBrstpol != dffrstpol)
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goto reject_ffH;
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}
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ffH = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux)
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ffHrstmux = dffrstmux;
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// H does not have a CE-like (hold) input
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if (dffcemux)
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reject;
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// Reset signal of H (IRSTBOT) shared with B
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if ((ffBrstmux != NULL) != (ffHrstmux != NULL))
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reject;
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if (ffBrstmux) {
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if (port(ffBrstmux, \S) != port(ffHrstmux, \S))
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reject;
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if (ffBrstpol != dffrstpol)
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reject;
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}
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sigH = dffQ;
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}
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}
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if (0) {
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reject_ffH: ;
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}
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sigO = sigH;
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endcode
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@ -274,26 +278,46 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c
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}
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endcode
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code argQ ffCD ffCDcemux ffCDrstmux ffCDcepol ffCDrstpol sigCD clock clock_pol
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code argQ ffCD ffCDcemux ffCDcepol ffCDrstpol sigCD clock clock_pol
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if (!sigCD.empty() &&
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(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
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argQ = sigCD;
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subpattern(in_dffe);
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if (dff) {
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ffCD = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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if (dffrstmux) {
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ffCDrstmux = dffrstmux;
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ffCDrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffCDcemux = dffcemux;
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ffCDcepol = dffcepol;
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}
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// Reset signal of C (IRSTTOP) and D (IRSTBOT)
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// shared with A and B
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if ((ffArstmux != NULL) != (dffrstmux != NULL))
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goto reject_ffCD;
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if ((ffBrstmux != NULL) != (dffrstmux != NULL))
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goto reject_ffCD;
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if (ffArstmux) {
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if (port(ffArstmux, \S) != port(dffrstmux, \S))
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goto reject_ffCD;
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if (ffArstpol != dffrstpol)
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goto reject_ffCD;
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}
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if (ffBrstmux) {
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if (port(ffBrstmux, \S) != port(dffrstmux, \S))
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goto reject_ffCD;
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if (ffBrstpol != dffrstpol)
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goto reject_ffCD;
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}
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ffCD = dff;
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clock = dffclock;
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clock_pol = dffclock_pol;
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sigCD = dffD;
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}
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}
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if (0) {
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reject_ffCD: ;
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}
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endcode
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code sigCD
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@ -418,6 +442,9 @@ arg argD argQ clock clock_pol
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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match ffcemux
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@ -434,7 +461,7 @@ match ffcemux
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index <SigBit> port(ffcemux, BA)[offset] === argD[0]
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// Check that the rest of argD is present
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filter GetSize(BA) >= offset + GetSize(argD)
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filter GetSize(port(ffcemux, BA)) >= offset + GetSize(argD)
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filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
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set ffoffset offset
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@ -448,12 +475,6 @@ code argD argQ
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dffcemux = ffcemux;
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if (ffcemux) {
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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if (ffoffset + GetSize(argD) > GetSize(BA))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (BA[ffoffset+i] != argD[i])
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reject;
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SigSpec Y = port(ffcemux, \Y);
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argQ = argD;
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argD.replace(BA, Y);
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@ -480,7 +501,7 @@ match ffrstmux
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// Check that offset is consistent
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filter !ffcemux || ffoffset == offset
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// Check that the rest of argD is present
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filter GetSize(AB) >= offset + GetSize(argD)
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filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
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filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
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set ffoffset offset
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@ -519,8 +540,6 @@ match ff
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filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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set ffoffset offset
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semioptional
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endmatch
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code argQ
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@ -531,7 +550,6 @@ code argQ
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if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
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reject;
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}
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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if (!ffcemux) {
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@ -540,8 +558,6 @@ code argQ
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}
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for (auto c : argQ.chunks()) {
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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