riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Also add first.Q to chain_bits since variable length

This commit is contained in:
Eddie Hung 2019-08-23 18:14:06 -07:00
parent 70ce3d0670
commit ee9f6e6243
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
passes/pmgen/xilinx_srl.pmg
View File

@ -196,6 +196,7 @@ code clk_port en_port
en_port = \EN;
else log_abort();
chain_bits.insert(port(first, \Q)[slice]);
chain.emplace_back(first, slice);
subpattern(tail);
finally