mirror of https://github.com/YosysHQ/yosys.git
Rename dffmuxext -> dffmux, also remove constants in dff+mux
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3a8582081e
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@ -27,7 +27,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
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PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg
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PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmuxext.pmg
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PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg
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passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
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@ -60,7 +60,7 @@ struct PeepoptPass : public Pass {
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peepopt_pm pm(module, module->selected_cells());
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pm.run_shiftmul();
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pm.run_muldiv();
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pm.run_dffmuxext();
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pm.run_dffmux();
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}
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}
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}
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@ -0,0 +1,89 @@
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pattern dffmux
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state <IdString> muxAB
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match dff
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select dff->type == $dff
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select GetSize(port(dff, \D)) > 1
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endmatch
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match mux
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select mux->type == $mux
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select GetSize(port(mux, \Y)) > 1
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choice <IdString> AB {\A, \B}
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//select port(mux, AB)[GetSize(port(mux, \Y))-1].wire
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index <SigSpec> port(mux, \Y) === port(dff, \D)
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, BA) === port(dff, \Q)
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set muxAB AB
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endmatch
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code
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SigSpec &D = mux->connections_.at(muxAB);
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SigSpec &Q = dff->connections_.at(\Q);
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int width = GetSize(D);
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SigSpec AB = port(mux, muxAB);
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if (AB[width-1] == AB[width-2]) {
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did_something = true;
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SigBit sign = D[width-1];
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bool is_signed = sign.wire;
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int i;
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for (i = width-1; i >= 2; i--) {
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if (!is_signed) {
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module->connect(Q[i], sign);
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if (D[i-1] != sign)
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break;
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}
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else {
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module->connect(Q[i], Q[i-1]);
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if (D[i-2] != sign)
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break;
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}
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}
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mux->connections_.at(\A).remove(i, width-i);
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mux->connections_.at(\B).remove(i, width-i);
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mux->connections_.at(\Y).remove(i, width-i);
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mux->fixup_parameters();
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dff->connections_.at(\D).remove(i, width-i);
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dff->connections_.at(\Q).remove(i, width-i);
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dff->fixup_parameters();
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log("dffmux pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i);
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accept;
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}
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else {
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int count = 0;
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for (int i = width-1; i >= 0; i--) {
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if (AB[i].wire)
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continue;
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Wire *w = Q[i].wire;
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auto it = w->attributes.find(\init);
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State init;
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if (it != w->attributes.end())
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init = it->second[Q[i].offset];
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else
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init = State::Sx;
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if (init == State::Sx || init == AB[i].data) {
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count++;
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module->connect(Q[i], AB[i]);
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mux->connections_.at(\A).remove(i);
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mux->connections_.at(\B).remove(i);
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mux->connections_.at(\Y).remove(i);
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dff->connections_.at(\D).remove(i);
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dff->connections_.at(\Q).remove(i);
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}
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}
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if (count > 0) {
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did_something = true;
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mux->fixup_parameters();
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dff->fixup_parameters();
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}
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log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count);
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accept;
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}
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endcode
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@ -1,55 +0,0 @@
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pattern dffmuxext
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state <IdString> muxAB
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match dff
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select dff->type == $dff
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select GetSize(port(dff, \D)) > 1
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endmatch
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match mux
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select mux->type == $mux
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select GetSize(port(mux, \Y)) > 1
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choice <IdString> AB {\A, \B}
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//select port(mux, AB)[GetSize(port(mux, \Y))-1].wire
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index <SigSpec> port(mux, \Y) === port(dff, \D)
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, BA) === port(dff, \Q)
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filter port(mux, AB)[GetSize(port(mux, \Y))-1] == port(mux, AB)[GetSize(port(mux, \Y))-2]
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set muxAB AB
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endmatch
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code
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did_something = true;
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SigSpec &D = mux->connections_.at(muxAB);
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SigSpec &Q = dff->connections_.at(\Q);
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int width = GetSize(D);
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SigBit sign = D[width-1];
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bool is_signed = sign.wire;
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int i;
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for (i = width-1; i >= 2; i--) {
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if (!is_signed) {
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module->connect(Q[i], sign);
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if (D[i-1] != sign)
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break;
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}
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else {
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module->connect(Q[i], Q[i-1]);
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if (D[i-2] != sign)
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break;
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}
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}
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mux->connections_.at(\A).remove(i, width-i);
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mux->connections_.at(\B).remove(i, width-i);
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mux->connections_.at(\Y).remove(i, width-i);
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mux->fixup_parameters();
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dff->connections_.at(\D).remove(i, width-i);
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dff->connections_.at(\Q).remove(i, width-i);
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dff->fixup_parameters();
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log("dffmuxext pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i);
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accept;
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endcode
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