mirror of https://github.com/YosysHQ/yosys.git
Remove debug
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@ -83,7 +83,6 @@ endmatch
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code clock sigM sigP
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if (ffM) {
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log_warning("M FOUND!\n");
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sigM = port(ffM, \Q);
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for (auto b : sigM)
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if (b.wire->get_bool_attribute(\keep))
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