mirror of https://github.com/YosysHQ/yosys.git
Tidy up ice40_dsp some more
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@ -219,10 +219,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
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if (st.ffO) {
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if (st.ffO_hilo)
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cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
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else
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if (st.ffO_lo)
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
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else
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cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
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st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
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cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
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@ -3,7 +3,7 @@ pattern ice40_dsp
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state <SigBit> clock
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state <bool> clock_pol cd_signed
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state <SigSpec> sigA sigB sigCD sigH sigO
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state <Cell*> addAB muxAB ffO
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state <Cell*> addAB muxAB
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match mul
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select mul->type.in($mul, \SB_MAC16)
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@ -202,21 +202,21 @@ code muxAB sigO
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sigO = port(muxAB, \Y);
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endcode
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match ffO_hilo
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match ffO
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// Ensure that register is not already used
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if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
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if nusers(sigO) == 2
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select ffO_hilo->type.in($dff)
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filter GetSize(port(ffO_hilo, \D)) >= GetSize(sigO)
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slice offset GetSize(port(ffO_hilo, \D))
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filter offset+GetSize(sigO) <= GetSize(port(ffO_hilo, \D)) && port(ffO_hilo, \D).extract(offset, GetSize(sigO)) == sigO
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select ffO->type.in($dff)
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filter GetSize(port(ffO, \D)) >= GetSize(sigO)
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slice offset GetSize(port(ffO, \D))
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filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
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optional
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endmatch
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match ffO_lo
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if !ffO_hilo && GetSize(sigO) > 16
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if !ffO && GetSize(sigO) > 16
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// Ensure that register is not already used
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if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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@ -230,11 +230,10 @@ match ffO_lo
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endmatch
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code ffO clock clock_pol sigO sigCD cd_signed
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ffO = nullptr;
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if (ffO_hilo)
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ffO = ffO_hilo;
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else if (ffO_lo)
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if (ffO_lo) {
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log_assert(!ffO);
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ffO = ffO_lo;
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}
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if (ffO) {
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for (auto b : port(ffO, \Q))
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if (b.wire->get_bool_attribute(\keep))
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