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ffAmuxAB -> ffAenpol

This commit is contained in:
Eddie Hung 2019-09-05 21:28:28 -07:00
parent 5a2fc6fcb5
commit 53ca536d67
2 changed files with 9 additions and 6 deletions
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5
passes/pmgen/xilinx_dsp.cc
View File

@ -83,9 +83,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
A.replace(Q, D);
if (st.ffAmux) {
SigSpec Y = st.ffAmux->getPort("\\Y");
SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B");
A.replace(Y, AB);
cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
SigSpec S = st.ffAmux->getPort("\\S");
cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
}
else
cell->setPort("\\CEA2", State::S1);

10
passes/pmgen/xilinx_dsp.pmg
View File

@ -2,7 +2,8 @@ pattern xilinx_dsp
state <SigBit> clock
state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
state <bool> ffAenpol
match dsp
select dsp->type.in(\DSP48E1)
@ -69,9 +70,10 @@ match ffAmux
filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
slice offset GetSize(port(ffAmux, \Y))
filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
choice <IdString> AB {\A, \B}
filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux
set ffAmuxAB AB
choice <IdString> BA {\B, \A}
filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux
define <bool> pol (BA == \B)
set ffAenpol pol
semioptional
endmatch