mirror of https://github.com/YosysHQ/yosys.git
276 lines
7.1 KiB
Plaintext
276 lines
7.1 KiB
Plaintext
pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
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state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
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state <bool> ffAenpol
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigffAmux sigB sigffBmux sigM
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sigA = port(dsp, \A);
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int i;
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for (i = GetSize(sigA)-1; i > 0; i--)
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if (sigA[i] != sigA[i-1])
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break;
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// Do not remove non-const sign bit
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if (sigA[i].wire)
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++i;
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sigA.remove(i, GetSize(sigA)-i);
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sigB = port(dsp, \B);
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for (i = GetSize(sigB)-1; i > 0; i--)
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if (sigB[i] != sigB[i-1])
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break;
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// Do not remove non-const sign bit
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if (sigB[i].wire)
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++i;
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sigB.remove(i, GetSize(sigB)-i);
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SigSpec P = port(dsp, \P);
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// Only care about those bits that are used
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for (i = 0; i < GetSize(P); i++) {
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if (nusers(P[i]) <= 1)
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break;
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sigM.append(P[i]);
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}
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log_assert(nusers(P.extract_end(i)) <= 1);
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//if (GetSize(sigM) <= 10)
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// reject;
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endcode
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match ffA
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if param(dsp, \AREG).as_int() == 0
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select ffA->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffA, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffA, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code sigA sigffAmux clock
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if (ffA) {
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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clock = port(ffA, \CLK).as_bit();
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sigffAmux = sigA;
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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}
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endcode
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match ffAmux
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if ffA
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select ffAmux->type.in($mux)
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filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
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slice offset GetSize(port(ffAmux, \Y))
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filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
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choice <IdString> BA {\B, \A}
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filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux
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define <bool> pol (BA == \B)
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set ffAenpol pol
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semioptional
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endmatch
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match ffB
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if param(dsp, \BREG).as_int() == 0
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select ffB->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffB, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
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slice offset GetSize(port(ffB, \Q))
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filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
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optional
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endmatch
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code sigB sigffBmux clock
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if (ffB) {
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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sigffBmux = sigB;
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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}
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endcode
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match ffBmux
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if ffB
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select ffBmux->type.in($mux)
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filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB)
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slice offset GetSize(port(ffBmux, \Y))
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filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, \Y).extract(offset, GetSize(sigB)) == sigB
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffBmux) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, AB).extract(offset, GetSize(sigffBmux)) == sigffBmux
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set ffBmuxAB AB
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semioptional
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endmatch
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match ffMmux
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select ffMmux->type.in($mux)
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select nusers(port(ffMmux, \Y)) == 2
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filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM)
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choice <IdString> AB {\A, \B}
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filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
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filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
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set ffMmuxAB AB
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optional
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endmatch
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code sigM
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if (ffMmux)
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sigM = port(ffMmux, \Y);
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endcode
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match ffM
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if param(dsp, \MREG).as_int() == 0
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select ffM->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffM, \CLK_POLARITY).as_bool()
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select nusers(port(ffM, \D)) == 2
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filter GetSize(port(ffM, \D)) <= GetSize(sigM)
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filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
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filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
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// Check ffMmux (when present) is a $dff enable mux
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filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMmuxAB == \A ? \B : \A)
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optional
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endmatch
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code clock sigM sigP
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if (ffM) {
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sigM = port(ffM, \Q);
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for (auto b : sigM)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffM, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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// Cannot have ffMmux enable mux without ffM
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else if (ffMmux)
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reject;
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sigP = sigM;
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endcode
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
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select postAdd->type.in($add)
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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filter ffMmux || nusers(port(postAdd, AB)) == 2
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filter !ffMmux || nusers(port(postAdd, AB)) == 3
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filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
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filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
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filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
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set postAddAB AB
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optional
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endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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// TODO for DSP48E1, which will have sign extended inputs/outputs
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//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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//int actual_mul_width = GetSize(sigP);
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//int actual_acc_width = GetSize(sigC);
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//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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// reject;
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
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// reject;
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sigP = port(postAdd, \Y);
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}
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endcode
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match ffPmux
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select ffPmux->type.in($mux)
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select nusers(port(ffPmux, \Y)) == 2
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filter GetSize(port(ffPmux, \Y)) <= GetSize(sigP)
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choice <IdString> AB {\A, \B}
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filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
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filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
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set ffPmuxAB AB
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optional
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endmatch
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code sigP
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if (ffPmux)
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sigP.replace(port(ffPmux, ffPmuxAB), port(ffPmux, \Y));
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endcode
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match ffP
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if param(dsp, \PREG).as_int() == 0
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select ffP->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffP, \D)) >= GetSize(sigP)
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slice offset GetSize(port(ffP, \D))
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filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
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// Check ffPmux (when present) is a $dff enable mux
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filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPmuxAB == \A ? \B : \A)
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optional
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endmatch
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code ffP sigP clock
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if (ffP) {
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for (auto b : port(ffP, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffP, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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sigP.replace(port(ffP, \D), port(ffP, \Q));
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}
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// Cannot have ffPmux enable mux without ffP
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else if (ffPmux)
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reject;
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endcode
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match postAddMux
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if postAdd
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if ffP
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select postAddMux->type.in($mux)
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select nusers(port(postAddMux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(postAddMux, AB) === sigP
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index <SigSpec> port(postAddMux, \Y) === sigC
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set postAddMuxAB AB
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optional
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endmatch
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code sigC
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if (postAddMux)
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code
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accept;
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endcode
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