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@ -495,9 +495,9 @@ struct XilinxDspPass : public Pass {
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log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
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log("used to override the existing accumulation result with a new value.\n");
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log("\n");
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log("'PCOUT' -> 'PCIN' cascading is detected for 'P' -> 'C' connections, where 'P' is\n");
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log("is right-shifted by 18-bits and used as an input to the post-adder (a common\n");
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log("pattern for summing partial products).\n");
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log("Use of the dedicated 'PCOUT' -> 'PCIN' path is detected for 'P' -> 'C' connections\n");
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log("where 'P' is right-shifted by 18-bits and used as an input to the post-adder (a\n");
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log("pattern common for summing partial products to implement wide multiplies).\n");
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log("\n");
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log("Not currently supported: reset (RST*) inputs on any register.\n");
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log("\n");
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