mirror of https://github.com/YosysHQ/yosys.git
Refactor using subpattern in_dffe
This commit is contained in:
Eddie Hung
parent
e68507a716
commit
04bc287271
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@ -7,11 +7,21 @@ state <IdString> postAddAB postAddMuxAB
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state <bool> ffAenpol ffADenpol ffBenpol ffCenpol ffDenpol ffMenpol ffPenpol
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux
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// subpattern
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state <SigSpec> dffQ
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state <bool> dffenpol_
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udata <SigSpec> dffD
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udata <SigBit> dffclock
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udata <Cell*> dff dffmux
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udata <bool> dffenpol
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code unextend sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM
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code unextend sigA sigB sigC sigD sigM
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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@ -39,60 +49,24 @@ code unextend sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY si
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log_assert(nusers(P.extract_end(i)) <= 1);
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//if (GetSize(sigM) <= 10)
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// reject;
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sigffAmuxY = SigSpec();
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sigffBmuxY = SigSpec();
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sigffCmuxY = SigSpec();
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sigffDmuxY = SigSpec();
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endcode
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match ffAD
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if param(dsp, \ADREG).as_int() == 0
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select ffAD->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffAD, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffAD, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffAD, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffAD, \Q))
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filter port(ffAD, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code sigA sigffAmuxY clock
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if (ffAD) {
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for (auto b : port(ffAD, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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clock = port(ffAD, \CLK).as_bit();
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SigSpec A = sigA;
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A.replace(port(ffAD, \Q), port(ffAD, \D));
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// Only search for ffAmux if ffA.Q has at
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// least 3 users (ffA, dsp, ffAmux) and
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// its ffA.D only has two (ffA, ffAmux)
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if (nusers(sigA) >= 3 && nusers(A) == 2)
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sigffAmuxY = sigA;
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sigA = std::move(A);
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code dffQ ffAD ffADmux ffADenpol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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dffQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffAD = dff;
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clock = dffclock;
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if (dffmux) {
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ffADmux = dffmux;
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ffADenpol = dffenpol;
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}
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sigA = dffD;
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}
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}
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endcode
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match ffADmux
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if !sigffAmuxY.empty()
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select ffADmux->type.in($mux)
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index <SigSpec> port(ffADmux, \Y) === port(ffAD, \D)
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filter GetSize(port(ffADmux, \Y)) >= GetSize(sigA)
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slice offset GetSize(port(ffADmux, \Y))
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filter offset+GetSize(sigA) <= GetSize(port(ffADmux, \Y))
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filter port(ffADmux, \Y).extract(offset, GetSize(sigA)) == sigA
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffAmuxY) <= GetSize(port(ffADmux, \Y))
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filter port(ffADmux, AB).extract(offset, GetSize(sigffAmuxY)) == sigffAmuxY
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define <bool> pol (AB == \A)
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set ffADenpol pol
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optional
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endmatch
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match preAdd
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if sigD.empty() || sigD.is_fully_zero()
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// Ensure that preAdder not already used
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@ -123,169 +97,66 @@ code sigA sigD
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}
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endcode
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match ffA
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if !preAdd
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if param(dsp, \AREG).as_int() == 0
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select ffA->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffA, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffA, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q))
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filter port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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endmatch
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code sigA sigffAmuxY clock
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if (ffA) {
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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clock = port(ffA, \CLK).as_bit();
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SigSpec A = sigA;
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A.replace(port(ffA, \Q), port(ffA, \D));
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// Only search for ffAmux if ffA.Q has at
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// least 3 users (ffA, dsp, ffAmux) and
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// its ffA.D only has two (ffA, ffAmux)
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if (nusers(sigA) >= 3 && nusers(A) == 2)
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sigffAmuxY = sigA;
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sigA = std::move(A);
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code dffQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
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// Only search for ffA if there was a pre-adder
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// (otherwise ffA would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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dffQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA = dff;
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clock = dffclock;
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if (dffmux) {
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ffAmux = dffmux;
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ffAenpol = dffenpol;
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}
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sigA = dffD;
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}
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}
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}
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else if (!preAdd) {
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sigffAmuxY = SigSpec();
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}
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endcode
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match ffAmux
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if !sigffAmuxY.empty()
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select ffAmux->type.in($mux)
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index <SigSpec> port(ffAmux, \Y) === port(ffA, \D)
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filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
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slice offset GetSize(port(ffAmux, \Y))
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filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y))
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filter port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffAmuxY) <= GetSize(port(ffAmux, \Y))
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filter port(ffAmux, AB).extract(offset, GetSize(sigffAmuxY)) == sigffAmuxY
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define <bool> pol (AB == \A)
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set ffAenpol pol
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optional
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endmatch
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code ffA ffAmux ffAenpol ffAD ffADmux
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// Move AD register to A if no pre-adder
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if (!ffA && !preAdd && ffAD) {
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ffA = ffAD;
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ffAmux = ffADmux;
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA && !ffAmux);
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std::swap(ffA, ffAD);
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std::swap(ffAmux, ffADmux);
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ffAenpol = ffADenpol;
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ffAD = nullptr;
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ffADmux = nullptr;
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}
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endcode
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match ffB
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if param(dsp, \BREG).as_int() == 0
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select ffB->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffB, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
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slice offset GetSize(port(ffB, \Q))
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filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q))
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filter port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
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optional
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endmatch
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code sigB sigffBmuxY clock
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if (ffB) {
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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SigSpec B = sigB;
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B.replace(port(ffB, \Q), port(ffB, \D));
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// Only search for ffBmux if ffB.Q has at
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// least 3 users (ffB, dsp, ffBmux) and
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// its ffB.D only has two (ffB, ffBmux)
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if (nusers(sigB) >= 3 && nusers(B) == 2)
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sigffBmuxY = sigB;
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sigB = std::move(B);
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code dffQ ffB ffBmux ffBenpol sigB clock
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if (param(dsp, \BREG).as_int() == 0) {
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dffQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB = dff;
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clock = dffclock;
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if (dffmux) {
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ffBmux = dffmux;
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ffBenpol = dffenpol;
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}
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sigB = dffD;
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}
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}
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endcode
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match ffBmux
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if !sigffBmuxY.empty()
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select ffBmux->type.in($mux)
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index <SigSpec> port(ffBmux, \Y) === port(ffB, \D)
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filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB)
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slice offset GetSize(port(ffBmux, \Y))
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filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y))
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filter port(ffBmux, \Y).extract(offset, GetSize(sigB)) == sigB
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffBmuxY) <= GetSize(port(ffBmux, \Y))
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filter port(ffBmux, AB).extract(offset, GetSize(sigffBmuxY)) == sigffBmuxY
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define <bool> pol (AB == \A)
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set ffBenpol pol
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optional
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endmatch
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match ffD
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if param(dsp, \DREG).as_int() == 0
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select ffD->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffD, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffD, \Q)) >= GetSize(sigD)
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slice offset GetSize(port(ffD, \Q))
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filter offset+GetSize(sigD) <= GetSize(port(ffD, \Q))
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filter port(ffD, \Q).extract(offset, GetSize(sigD)) == sigD
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optional
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endmatch
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code sigD sigffDmuxY clock
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if (ffD) {
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for (auto b : port(ffD, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffD, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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SigSpec D = sigD;
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D.replace(port(ffD, \Q), port(ffD, \D));
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// Only search for ffDmux if ffD.Q has at
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// least 3 users (ffD, dsp, ffDmux) and
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// its ffD.D only has two (ffD, ffDmux)
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if (nusers(sigD) >= 3 && nusers(D) == 2)
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sigffDmuxY = sigD;
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sigD = std::move(D);
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code dffQ ffD ffDmux ffDenpol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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dffQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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if (dffmux) {
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ffDmux = dffmux;
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ffDenpol = dffenpol;
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}
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sigD = dffD;
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}
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}
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endcode
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match ffDmux
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if !sigffDmuxY.empty()
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select ffDmux->type.in($mux)
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index <SigSpec> port(ffDmux, \Y) === port(ffD, \D)
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filter GetSize(port(ffDmux, \Y)) >= GetSize(sigD)
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slice offset GetSize(port(ffDmux, \Y))
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filter offset+GetSize(sigD) <= GetSize(port(ffDmux, \Y))
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filter port(ffDmux, \Y).extract(offset, GetSize(sigD)) == sigD
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffDmuxY) <= GetSize(port(ffDmux, \Y))
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filter port(ffDmux, AB).extract(offset, GetSize(sigffDmuxY)) == sigffDmuxY
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define <bool> pol (AB == \A)
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set ffDenpol pol
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optional
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endmatch
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match ffMmux
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if param(dsp, \MREG).as_int() == 0
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if nusers(sigM) == 2
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@ -496,56 +367,91 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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match ffC
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if param(dsp, \CREG).as_int() == 0
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select ffC->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffC, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffC, \Q)) >= GetSize(sigD)
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slice offset GetSize(port(ffC, \Q))
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filter offset+GetSize(sigC) <= GetSize(port(ffC, \Q))
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filter port(ffC, \Q).extract(offset, GetSize(sigC)) == sigC
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optional
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endmatch
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code sigC sigffCmuxY clock
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if (ffC) {
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for (auto b : port(ffC, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffC, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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SigSpec C = sigC;
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C.replace(port(ffC, \Q), port(ffC, \D));
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// Only search for ffCmux if ffC.Q has at
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// least 3 users (ffC, dsp, ffCmux) and
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// its ffC.D only has two (ffC, ffCmux)
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if (nusers(sigC) >= 3 && nusers(C) == 2)
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sigffCmuxY = sigC;
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sigC = std::move(C);
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code dffQ ffC ffCmux ffCenpol sigC clock
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if (param(dsp, \CREG).as_int() == 0) {
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dffQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffmux) {
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ffCmux = dffmux;
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ffCenpol = dffenpol;
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}
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sigC = dffD;
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}
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}
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endcode
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match ffCmux
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if !sigffCmuxY.empty()
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select ffCmux->type.in($mux)
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index <SigSpec> port(ffCmux, \Y) === port(ffC, \D)
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filter GetSize(port(ffCmux, \Y)) >= GetSize(sigC)
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slice offset GetSize(port(ffCmux, \Y))
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filter offset+GetSize(sigC) <= GetSize(port(ffCmux, \Y))
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filter port(ffCmux, \Y).extract(offset, GetSize(sigC)) == sigC
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(sigffCmuxY) <= GetSize(port(ffCmux, \Y))
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filter port(ffCmux, AB).extract(offset, GetSize(sigffCmuxY)) == sigffCmuxY
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define <bool> pol (AB == \A)
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set ffCenpol pol
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optional
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endmatch
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code
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accept;
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endcode
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subpattern in_dffe
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arg dffQ clock dffenpol_
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code
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dff = nullptr;
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dffmux = nullptr;
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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filter GetSize(port(ff, \Q)) >= GetSize(dffQ)
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slice offset GetSize(port(ff, \Q))
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filter offset+GetSize(dffQ) <= GetSize(port(ff, \Q))
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filter port(ff, \Q).extract(offset, GetSize(dffQ)) == dffQ
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semioptional
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endmatch
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code dffQ
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if (ff) {
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for (auto b : dffQ)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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else
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dffclock = port(ff, \CLK);
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dff = ff;
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dffD = dffQ;
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dffD.replace(port(ff, \Q), port(ff, \D));
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// Only search for ffmux if ff.Q has at
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// least 3 users (ff, dsp, ffmux) and
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// its ff.D only has two (ff, ffmux)
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if (!(nusers(dffQ) >= 3 && nusers(dffD) == 2))
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dffQ = SigSpec();
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}
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else
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dffQ = SigSpec();
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endcode
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match ffmux
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if !dffQ.empty()
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select ffmux->type.in($mux)
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index <SigSpec> port(ffmux, \Y) === port(ff, \D)
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filter GetSize(port(ffmux, \Y)) >= GetSize(dffD)
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slice offset GetSize(port(ffmux, \Y))
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filter offset+GetSize(dffD) <= GetSize(port(ffmux, \Y))
|
||||
filter port(ffmux, \Y).extract(offset, GetSize(dffD)) == dffD
|
||||
choice <IdString> AB {\A, \B}
|
||||
filter offset+GetSize(dffQ) <= GetSize(port(ffmux, \Y))
|
||||
filter port(ffmux, AB).extract(offset, GetSize(dffQ)) == dffQ
|
||||
define <bool> pol (AB == \A)
|
||||
set dffenpol_ pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code
|
||||
if (ffmux) {
|
||||
dffmux = ffmux;
|
||||
dffenpol = dffenpol_;
|
||||
dffD = port(ffmux, dffenpol ? \B : \A);
|
||||
}
|
||||
endcode
|
||||
|
|
|
|||
Loading…
Reference in New Issue