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Fix width of D

This commit is contained in:
Eddie Hung 2019-09-19 18:08:46 -07:00
parent 2f98f9deee
commit c83a667555
1 changed files with 1 additions and 1 deletions
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2
passes/pmgen/xilinx_dsp.cc
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@ -48,7 +48,7 @@ static Cell* addDsp(Module *module) {
cell->setParam(ID(USE_SIMD), Const("ONE48"));
cell->setParam(ID(USE_DPORT), Const("FALSE"));
cell->setPort(ID(D), Const(0, 24));
cell->setPort(ID(D), Const(0, 25));
cell->setPort(ID(INMODE), Const(0, 5));
cell->setPort(ID(ALUMODE), Const(0, 4));
cell->setPort(ID(OPMODE), Const(0, 7));