mirror of https://github.com/YosysHQ/yosys.git
Fine tune xilinx_dsp pattern matcher
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@ -76,8 +76,9 @@ match ffM
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select param(ffM, \CLK_POLARITY).as_bool()
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select nusers(port(ffM, \D)) == 2
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//index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?!
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filter GetSize(port(ffM, \D)) <= GetSize(sigM)
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filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
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filter nusers(sigM.extract_end(param(ffM, \WIDTH).as_int())) == 1
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filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
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optional
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endmatch
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@ -88,7 +89,7 @@ code clock sigM sigP
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffB, \CLK).as_bit();
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SigBit c = port(ffM, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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@ -102,10 +103,11 @@ endcode
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match addA
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select addA->type.in($add)
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select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
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index <int> nusers(port(addA, \A)) === 2
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//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int())
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filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP)
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filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int())
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select nusers(port(addA, \A)) == 2
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//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int()) // TODO: Why doesn't this work!?!
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filter GetSize(port(addA, \A)) <= GetSize(sigP)
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filter port(addA, \A) == sigP.extract(0, GetSize(port(addA, \A)))
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filter nusers(sigP.extract_end(GetSize(port(addA, \A)))) <= 1
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optional
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endmatch
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@ -114,9 +116,10 @@ match addB
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select addB->type.in($add, $sub)
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select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
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index <int> nusers(port(addB, \B)) === 2
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//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
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filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
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filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int())
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//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int()) // TODO: Why doesn't this work!?!
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filter GetSize(port(addB, \B)) <= GetSize(sigP)
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filter port(addB, \B) == sigP.extract(0, GetSize(port(addB, \B)))
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filter nusers(sigP.extract_end(GetSize(port(addB, \B)))) <= 1
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optional
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endmatch
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@ -135,12 +138,13 @@ code addAB sigC sigP
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if (!opmodeZ.is_fully_zero())
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reject;
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int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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int actual_mul_width = GetSize(sigP);
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int actual_acc_width = GetSize(sigC);
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// TODO for DSP48E1, which will have sign extended inputs/outputs
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//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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//int actual_mul_width = GetSize(sigP);
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//int actual_acc_width = GetSize(sigC);
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if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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reject;
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//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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// reject;
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
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// reject;
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