mirror of https://github.com/YosysHQ/yosys.git
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
This commit is contained in:
Eddie Hung
parent
1844498c5f
commit
ed187ef1cf
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@ -22,8 +22,9 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
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# --------------------------------------
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OBJS += passes/pmgen/xilinx_dsp.o
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passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h
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passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
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# --------------------------------------
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@ -25,6 +25,7 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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#include "passes/pmgen/xilinx_dsp_cascade_pm.h"
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static Cell* addDsp(Module *module) {
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Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));
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@ -253,9 +254,9 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
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}
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void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp;
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auto &st = pm.st_xilinx_dsp_pack;
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#if 1
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log("\n");
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@ -487,9 +488,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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cell->setPort(ID(P), P);
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bit_to_driver.insert(std::make_pair(P[0], cell));
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bit_to_driver.insert(std::make_pair(P[17], cell));
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pm.blacklist(cell);
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}
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@ -508,7 +506,7 @@ struct XilinxDspPass : public Pass {
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log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
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log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
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log("used to override the current accumulation result with a new value, which will\n");
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log("be added to the multiplier result to form the next accumulation result.\n");
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log("be added to the multiplier result to form the next accumulation result.\n");
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log("\n");
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log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
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log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n");
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@ -545,52 +543,10 @@ struct XilinxDspPass : public Pass {
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pack_xilinx_simd(module, module->selected_cells());
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xilinx_dsp_pm pm(module, module->selected_cells());
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dict<SigBit, Cell*> bit_to_driver;
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auto f = [&bit_to_driver](xilinx_dsp_pm &pm){ pack_xilinx_dsp(bit_to_driver, pm); };
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pm.run_xilinx_dsp(f);
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pm.run_xilinx_dsp_pack(pack_xilinx_dsp);
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auto &unextend = pm.ud_xilinx_dsp.unextend;
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// Look for ability to convert C input from another DSP into PCIN
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// NB: Needs to be done after pattern matcher has folded all
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// $add cells into the DSP
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for (auto cell : module->cells()) {
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if (cell->type != ID(DSP48E1))
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continue;
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if (cell->parameters.at(ID(CREG), State::S1).as_bool())
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continue;
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SigSpec &opmode = cell->connections_.at(ID(OPMODE));
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if (opmode.extract(4,3) != Const::from_string("011"))
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continue;
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SigSpec C = unextend(pm.sigmap(cell->getPort(ID(C))));
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if (!C[0].wire)
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continue;
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auto it = bit_to_driver.find(C[0]);
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if (it == bit_to_driver.end())
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continue;
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auto driver = it->second;
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SigSpec P = driver->getPort(ID(P));
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if (GetSize(P) >= GetSize(C) && P.extract(0, GetSize(C)) == C) {
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cell->setPort(ID(C), Const(0, 48));
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Wire *cascade = module->addWire(NEW_ID, 48);
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driver->setPort(ID(PCOUT), cascade);
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cell->setPort(ID(PCIN), cascade);
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opmode[6] = State::S0;
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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bit_to_driver.erase(it);
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}
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else if (GetSize(P) >= GetSize(C)+17 && P.extract(17, GetSize(C)) == C) {
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cell->setPort(ID(C), Const(0, 48));
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Wire *cascade = module->addWire(NEW_ID, 48);
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driver->setPort(ID(PCOUT), cascade);
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cell->setPort(ID(PCIN), cascade);
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opmode[6] = State::S1;
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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bit_to_driver.erase(it);
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}
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}
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xilinx_dsp_cascade_pm pmc(module, module->selected_cells());
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pmc.run_xilinx_dsp_cascade();
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}
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}
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} XilinxDspPass;
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@ -1,4 +1,4 @@
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pattern xilinx_dsp
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pattern xilinx_dsp_pack
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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@ -0,0 +1,94 @@
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pattern xilinx_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigSpec> sigC
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code
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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endcode
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match dsp_pcin
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select dsp_pcin->type.in(\DSP48E1)
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select !param(dsp_pcin, \CREG, State::S1).as_bool()
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select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(dsp_pcin, \C, SigSpec())) > 1
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select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0
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endmatch
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code sigC
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sigC = unextend(port(dsp_pcin, \C));
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endcode
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match dsp_pcout
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select dsp_pcout->type.in(\DSP48E1)
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select nusers(port(dsp_pcout, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout, \P)[0] === sigC[0]
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filter GetSize(port(dsp_pcin, \P)) >= GetSize(sigC)
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filter port(dsp_pcout, \P).extract(0, GetSize(sigC)) == sigC
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optional
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endmatch
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match dsp_pcout_shift17
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if !dsp_pcout
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select dsp_pcout_shift17->type.in(\DSP48E1)
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select nusers(port(dsp_pcout_shift17, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout_shift17, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout_shift17, \P)[17] === sigC[0]
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filter GetSize(port(dsp_pcout_shift17, \P)) >= GetSize(sigC)+17
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filter port(dsp_pcout_shift17, \P).extract(17, GetSize(sigC)) == sigC
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endmatch
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code
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Cell *dsp;
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if (dsp_pcout)
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dsp = dsp_pcout;
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else if (dsp_pcout_shift17)
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dsp = dsp_pcout_shift17;
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else log_abort();
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dsp_pcin->setPort(ID(C), Const(0, 48));
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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SigSpec opmode = param(dsp_pcin, \OPMODE, Const(0, 7));
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if (dsp_pcout)
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opmode[6] = State::S0;
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else if (dsp_pcout_shift17)
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opmode[6] = State::S1;
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else log_abort();
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(ID(OPMODE), opmode);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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if (nusers(port(dsp_pcin, \PCOUT, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp_pcin));
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blacklist(dsp_pcin);
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}
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if (nusers(port(dsp, \PCIN, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp));
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blacklist(dsp_pcout);
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}
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accept;
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endcode
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