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Always generate if no match

This commit is contained in:
Eddie Hung 2019-08-28 09:54:56 -07:00
parent 0ebe2c9831
commit c3e9627afe
1 changed files with 1 additions and 1 deletions
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2
passes/pmgen/xilinx_srl.pmg
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@ -142,7 +142,7 @@ match next
filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool())
filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool())
filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
generate 10
generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));