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Do not run xilinx_srl_pm in fixed loop

This commit is contained in:
Eddie Hung 2019-08-22 10:51:04 -07:00
parent 7188972645
commit 61639d5387
1 changed files with 24 additions and 28 deletions
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52
passes/pmgen/xilinx_srl.cc
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@ -202,34 +202,30 @@ struct XilinxSrlPass : public Pass {
log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
for (auto module : design->selected_modules()) {
bool did_something = false;
if (fixed)
do {
auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_fixed.minlen = minlen;
// TODO: How to get these automatically?
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
did_something = pm.run_fixed(run_fixed);
} while (did_something);
if (variable)
do {
auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_variable.minlen = minlen;
// Since `nusers` does not count module ports as a user,
// and since `sigmap` does not always make such ports
// the canonical signal.. need to maintain a pool these
// ourselves
for (auto p : module->ports) {
auto w = module->wire(p);
if (w->port_output)
for (auto b : pm.sigmap(w))
pm.ud_variable.output_bits.insert(b);
}
did_something = pm.run_variable(run_variable);
} while (did_something);
auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_fixed.minlen = minlen;
if (fixed) {
// TODO: How to get these automatically?
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
pm.run_fixed(run_fixed);
}
if (variable) {
// Since `nusers` does not count module ports as a user,
// and since `sigmap` does not always make such ports
// the canonical signal.. need to maintain a pool these
// ourselves
for (auto p : module->ports) {
auto w = module->wire(p);
if (w->port_output)
for (auto b : pm.sigmap(w))
pm.ud_variable.output_bits.insert(b);
}
pm.run_variable(run_variable);
}
}
}
} XilinxSrlPass;