riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Rename muxAB to postAddMux

This commit is contained in:
Eddie Hung 2019-09-03 16:24:59 -07:00
parent cd002ad3fb
commit 16316aa05d
2 changed files with 25 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
passes/pmgen/xilinx_dsp.cc
View File

@ -35,15 +35,15 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
#if 1
log("\n");
log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("postAdd: %s\n", log_id(st.postAdd, "--"));
log("muxAB: %s\n", log_id(st.muxAB, "--"));
log("ffP: %s\n", log_id(st.ffP, "--"));
log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("postAdd: %s\n", log_id(st.postAdd, "--"));
log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
log("ffP: %s\n", log_id(st.ffP, "--"));
//log("muxP: %s\n", log_id(st.muxP, "--"));
log("sigPused: %s\n", log_signal(st.sigPused));
log("sigPused: %s\n", log_signal(st.sigPused));
#endif
log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
@ -59,9 +59,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
SigSpec &opmode = cell->connections_.at("\\OPMODE");
if (st.ffP && st.muxAB) {
opmode[4] = st.muxAB->getPort("\\S");
pm.autoremove(st.muxAB);
if (st.ffP && st.postAddMux) {
opmode[4] = st.postAddMux->getPort("\\S");
pm.autoremove(st.postAddMux);
}
else if (st.ffP && C == P) {
C = SigSpec();

47
passes/pmgen/xilinx_dsp.pmg
View File

@ -3,8 +3,8 @@ pattern xilinx_dsp
state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigM sigMused sigP sigPused
state <Cell*> postAdd muxAB
state <IdString> postAddAB
state <Cell*> postAdd postAddMux
state <IdString> postAddAB postAddMuxAB
match dsp
select dsp->type.in(\DSP48E1)
@ -105,10 +105,9 @@ match postAdd
// Ensure that Z mux is not already used
if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
select postAdd->type.in($postAdd)
select postAdd->type.in($add)
select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool()
choice <IdString> AB {\A, \B}
define <IdString> AB_WIDTH (AB == \A ? \A_WIDTH : \B_WIDTH)
select nusers(port(postAdd, AB)) == 2
filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
@ -172,39 +171,21 @@ code ffP sigP clock
}
endcode
match muxA
match postAddMux
if postAdd
select muxA->type.in($mux)
select nusers(port(muxA, \Y)) == 2
index <SigSpec> port(muxA, \A) === sigP
index <SigSpec> port(muxA, \Y) === sigC
if ffP
select postAddMux->type.in($mux)
select nusers(port(postAddMux, \Y)) == 2
choice <IdString> AB {\A, \B}
index <SigSpec> port(postAddMux, AB) === sigP
index <SigSpec> port(postAddMux, \Y) === sigC
set postAddMuxAB AB
optional
endmatch
match muxB
if postAdd
select muxB->type.in($mux)
select nusers(port(muxB, \Y)) == 2
index <SigSpec> port(muxB, \B) === sigP
index <SigSpec> port(muxB, \Y) === sigC
optional
endmatch
code sigC muxAB
if (muxA) {
muxAB = muxA;
sigC = port(muxAB, \B);
}
if (muxB) {
muxAB = muxB;
sigC = port(muxAB, \A);
}
if (muxAB) {
// Ensure that postAdder is not used
SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3);
if (!opmodeZ.is_fully_zero())
reject;
}
code sigC
if (postAddMux)
sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
endcode
code