riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Tidy up

This commit is contained in:
Eddie Hung 2019-09-09 15:59:10 -07:00
parent 04bc287271
commit 5f8f0e1383
1 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
passes/pmgen/xilinx_dsp.pmg
View File

@ -390,11 +390,6 @@ endcode
subpattern in_dffe
arg dffQ clock dffenpol_
code
dff = nullptr;
dffmux = nullptr;
endcode
match ff
select ff->type.in($dff)
// DSP48E1 does not support clock inversion
@ -428,8 +423,10 @@ code dffQ
if (!(nusers(dffQ) >= 3 && nusers(dffD) == 2))
dffQ = SigSpec();
}
else
else {
dff = nullptr;
dffQ = SigSpec();
}
endcode
match ffmux
@ -454,4 +451,6 @@ code
dffenpol = dffenpol_;
dffD = port(ffmux, dffenpol ? \B : \A);
}
else
dffmux = nullptr;
endcode