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Perform D replacement properly

This commit is contained in:
Eddie Hung 2019-09-06 15:46:15 -07:00
parent 74eac76699
commit 5344bfe637
2 changed files with 11 additions and 7 deletions
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13
passes/pmgen/xilinx_dsp.cc
View File

@ -144,13 +144,22 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
cell->setParam("\\BREG", 1);
}
if (st.ffD) {
SigSpec D_ = cell->getPort("\\D");
SigSpec D = st.ffB->getPort("\\D");
SigSpec Q = st.ffB->getPort("\\Q");
D_.replace(Q, D);
if (st.ffDmux) {
SigSpec Y = st.ffDmux->getPort("\\Y");
SigSpec AB = st.ffDmux->getPort(st.ffDenpol ? "\\B" : "\\A");
SigSpec S = st.ffDmux->getPort("\\S");
cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
D_.replace(Y, AB);
cell->setPort("\\CED", st.ffDenpol ? S : pm.module->Not(NEW_ID, S));
}
else
cell->setPort("\\CED", State::S1);
cell->setPort("\\D", st.sigD);
cell->setPort("\\D", D_);
cell->setParam("\\DREG", 1);
}

5
passes/pmgen/xilinx_dsp.pmg
View File

@ -286,11 +286,6 @@ match ffDmux
optional
endmatch
code sigD
if (ffDmux)
sigD.replace(port(ffDmux, \Y), port(ffDmux, ffDenpol ? \B : \A));
endcode
match ffMmux
if param(dsp, \MREG).as_int() == 0
if nusers(sigM) == 2