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Cope with possibility that D could connect to Q on same cell

This commit is contained in:
Eddie Hung 2019-08-23 13:06:31 -07:00
parent cee30deef5
commit 242b3083ea
1 changed files with 1 additions and 1 deletions
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2
passes/pmgen/xilinx_srl.pmg
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@ -197,7 +197,7 @@ match next
select !next->has_keep_attr()
select !port(next, \D)[0].wire->get_bool_attribute(\keep)
slice idx GetSize(port(next, \Q))
select nusers(port(next, \Q)[idx]) == 3
select nusers(port(next, \Q)[idx]) <= 3
index <IdString> next->type === chain.back().first->type
index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]