mirror of https://github.com/YosysHQ/yosys.git
Add support for RSTM
This commit is contained in:
Eddie Hung
parent
fc7008671f
commit
ded805ae5d
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@ -269,7 +269,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("ffDmux: %s\n", log_id(st.ffDmux, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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log("ffMmux: %s\n", log_id(st.ffMmux, "--"));
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log("ffMcemux: %s\n", log_id(st.ffMcemux, "--"));
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log("ffMrstmux: %s\n", log_id(st.ffMrstmux, "--"));
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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@ -417,38 +418,48 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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cell->setParam("\\DREG", 1);
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}
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if (st.ffM) {
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if (st.ffMmux) {
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SigSpec S = st.ffMmux->getPort("\\S");
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if (st.ffMrstmux) {
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SigSpec S = st.ffMrstmux->getPort("\\S");
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cell->setPort("\\RSTM", st.ffMrstpol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort("\\RSTM", State::S0);
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if (st.ffMcemux) {
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SigSpec S = st.ffMcemux->getPort("\\S");
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cell->setPort("\\CEM", st.ffMcepol ? S : pm.module->Not(NEW_ID, S));
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pm.autoremove(st.ffMmux);
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}
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else
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cell->setPort("\\CEM", State::S1);
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SigSpec D = st.ffM->getPort("\\D");
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SigSpec Q = st.ffM->getPort("\\Q");
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P.replace(pm.sigmap(D), Q);
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st.ffM->connections_.at("\\Q").replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
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for (auto c : Q.chunks()) {
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auto it = c.wire->attributes.find("\\init");
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if (it == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset+c.width; i++) {
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log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
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it->second[i] = State::Sx;
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}
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}
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cell->setParam("\\MREG", State::S1);
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pm.autoremove(st.ffM);
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}
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if (st.ffP) {
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if (st.ffPrstmux) {
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SigSpec S = st.ffPrstmux->getPort("\\S");
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cell->setPort("\\RSTP", st.ffPrstpol ? S : pm.module->Not(NEW_ID, S));
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st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\RSTP", State::S0);
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if (st.ffPcemux) {
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SigSpec S = st.ffPcemux->getPort("\\S");
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cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));
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st.ffPcemux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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}
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else
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cell->setPort("\\CEP", State::S1);
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SigSpec D = st.ffP->getPort("\\D");
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SigSpec Q = st.ffP->getPort("\\Q");
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P.replace(pm.sigmap(D), Q);
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st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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for (auto c : Q.chunks()) {
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@ -4,14 +4,15 @@ state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffPcepol ffPrstpol
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffMrstpol ffPcepol ffPrstpol
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMmux ffP ffPcemux ffPrstmux
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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@ -159,7 +160,7 @@ code argQ ffD ffDmux ffDcepol sigD clock
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}
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endcode
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code argD ffM ffMmux ffMcepol sigM sigP clock
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code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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@ -167,8 +168,10 @@ code argD ffM ffMmux ffMcepol sigM sigP clock
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ffM = dff;
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clock = dffclock;
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if (dffcemux) {
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ffMmux = dffcemux;
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ffMcemux = dffcemux;
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ffMrstmux = dffrstmux;
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ffMcepol = dffcepol;
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ffMrstpol = dffrstpol;
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}
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sigM = dffQ;
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}
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@ -185,8 +188,8 @@ match postAdd
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select nusers(port(postAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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filter ffMmux || nusers(port(postAdd, AB)) == 2
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filter !ffMmux || nusers(port(postAdd, AB)) == 3
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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filter !ffMcemux || nusers(port(postAdd, AB)) == 3
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filter GetSize(unextend(port(postAdd, AB))) <= GetSize(sigP)
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filter unextend(port(postAdd, AB)) == sigP.extract(0, GetSize(unextend(port(postAdd, AB))))
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filter nusers(sigP.extract_end(GetSize(unextend(port(postAdd, AB))))) <= 1
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@ -214,10 +217,10 @@ endcode
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPcemux
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if ((ffMmux && !postAdd && nusers(sigP) == 3) ||
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// If ffMcemux and no postAdd new-value net must have exactly three users: ffMcemux, ffM and ffPcemux
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if ((ffMcemux && !postAdd && nusers(sigP) == 3) ||
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// Otherwise new-value net must have exactly two users: dsp and ffPcemux
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((!ffMmux || postAdd) && nusers(sigP) == 2)) {
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((!ffMcemux || postAdd) && nusers(sigP) == 2)) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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@ -347,107 +350,130 @@ subpattern out_dffe
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arg argD argQ clock
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arg unextend
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code
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dff = nullptr;
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endcode
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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select nusers(port(ffcemux, \Y)) == 2
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filter GetSize(port(ffcemux, \Y)) >= GetSize(argD)
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choice <IdString> BA {\B, \A}
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// new-value net must have exactly two users: (upstream) and ffcemux
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select nusers(port(ffcemux, BA)) == 2
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define <IdString> AB (BA == \B ? \A : \B)
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choice <IdString> AB {\A, \B}
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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slice offset GetSize(port(ffcemux, \Y))
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filter GetSize(unextend(port(ffcemux, BA))) <= GetSize(argD)
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filter unextend(port(ffcemux, BA)) == argD.extract(0, GetSize(unextend(port(ffcemux, BA))))
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// Remaining bits on argD must not have any other users
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filter nusers(argD.extract_end(GetSize(unextend(port(ffcemux, BA))))) <= 1
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define <bool> pol (AB == \A)
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigBit> port(ffcemux, BA)[offset] === argD[0]
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set ffoffset offset
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define <bool> pol (BA == \B)
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set ffcepol pol
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semioptional
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endmatch
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code argD argQ
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dffcemux = ffcemux;
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if (ffcemux) {
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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if (ffoffset + GetSize(argD) > GetSize(BA))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (BA[ffoffset+i] != argD[i])
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reject;
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SigSpec Y = port(ffcemux, \Y);
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argQ = argD;
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argD.replace(BA, Y);
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argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, \Y);
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argQ = port(ffcemux, ffcepol ? \A : \B);
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}
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else
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dffcemux = nullptr;
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endcode
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match ffrstmux
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if !argQ.empty()
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select ffrstmux->type.in($mux)
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// ffrstmux output must have two users: ffrstmux and ff.D
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select nusers(port(ffrstmux, \Y)) == 2
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filter GetSize(port(ffrstmux, \Y)) >= GetSize(argD)
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have exactly 2 users: ffrstmux, ffcemux/<upstream>
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select nusers(port(ffrstmux, AB)) == 2
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slice offset GetSize(port(ffrstmux, \Y))
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filter GetSize(port(ffrstmux, AB)) <= GetSize(argD)
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filter port(ffrstmux, AB) == argD.extract(0, GetSize(port(ffrstmux, AB)))
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// Remaining bits on argD must not have any other users
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filter nusers(argD.extract_end(GetSize(port(ffrstmux, AB)))) <= 1
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define <IdString> AB (BA == \B ? \A : \B)
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index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
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filter !ffcemux || ffoffset == offset
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set ffoffset offset
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define <bool> pol (AB == \A)
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set ffrstpol pol
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semioptional
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endmatch
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code argD argQ
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dffrstmux = ffrstmux;
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if (ffrstmux) {
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SigSpec AB = port(ffrstmux, ffcepol ? \A : \B);
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if (ffoffset + GetSize(argD) > GetSize(AB))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (AB[ffoffset+i] != argD[i])
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reject;
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SigSpec Y = port(ffrstmux, \Y);
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argD.replace(AB, Y);
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, \Y);
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}
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else {
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dffrstmux = nullptr;
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argQ = SigSpec();
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}
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endcode
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match ff_enable
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if !argQ.empty()
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select ff_enable->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff_enable, \D) === argD
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index <SigSpec> port(ff_enable, \Q) === argQ
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endmatch
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match ff
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if !ff_enable
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff, \D) === argD
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slice offset GetSize(port(ff, \D))
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index <SigSpec> port(ff, \D)[offset] === argD[0]
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filter (!ffcemux && !ffrstmux) || ffoffset == offset
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set ffoffset offset
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semioptional
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endmatch
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code
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if (ff_enable)
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dff = ff_enable;
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else
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dff = ff;
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if (dff) {
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dffQ = port(dff, \Q);
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code argQ
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if (ff) {
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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for (auto c : dffQ.chunks()) {
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SigSpec D = port(ff, \D);
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if (ffoffset + GetSize(argD) > GetSize(D))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (D[ffoffset+i] != argD[i])
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reject;
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SigSpec Q = port(ff, \Q);
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if (ffcemux) {
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for (int i = 0; i < GetSize(argQ); i++)
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if (Q[ffoffset+i] != argQ[i])
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reject;
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}
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else {
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argQ = argD;
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argQ.replace(D, Q);
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}
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for (auto c : argQ.chunks()) {
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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@ -455,13 +481,11 @@ code
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reject;
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}
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if (clock != SigBit()) {
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if (port(dff, \CLK) != clock)
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(dff, \CLK);
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}
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// No enable/reset mux possible without flop
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else if (ffcemux || ffrstmux)
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else if (dffcemux || dffrstmux)
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reject;
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endcode
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