cdec0cf28c
[script] add a custom variable to specify the path to openfpga shell script
2023-01-01 16:51:21 -08:00
c50daf273c
[script] add example script for using source command
2023-01-01 16:50:10 -08:00
d7a95a8ec2
[script] fixed some bugs
2022-12-30 18:30:52 -08:00
56a3e6e463
[test] reduce test size
2022-12-30 18:28:17 -08:00
93b020b0b3
[test] deploy new test to basic regression tests
2022-12-30 18:26:22 -08:00
ae11a4fbf2
[test] add a new test case
2022-12-30 18:25:15 -08:00
6973e9fb98
[script] add an example script for vpr standalone calls
2022-12-30 18:23:14 -08:00
c33b9f1b9b
[script] enable eval mode in tcl reg test
2022-12-02 12:07:27 -08:00
156fac9fec
[ci] deploy tcl test to ci
2022-12-02 11:46:14 -08:00
97c72c73f1
[test] add a small test to validate tcl integration
2022-12-02 11:43:46 -08:00
729a3a0249
[engine] tcl integration has initial success. Upload example scripts
2022-12-01 16:31:15 -08:00
9d8f4c1664
[script] format python codes
2022-11-21 14:21:31 -08:00
12d114bbae
[test] hit the bug of tileable rr_graph skip it
2022-11-05 10:52:04 -07:00
dc24e41c6b
[test] relax minW for counter128, as VPR's router degrades in routability
2022-11-03 19:48:13 -07:00
513f7800aa
[test] update golden outputs for no_cout_in_gsb testcase
2022-11-03 17:51:51 -07:00
a88bc2d4de
[test] update golden outputs for device4x4
2022-11-03 17:51:08 -07:00
5f74367c2e
[test] update golden for device1x1 no time stamp netlists
2022-11-03 17:48:40 -07:00
958ef37a83
Merge pull request #864 from yunuseryilmaz18/master
...
Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
2022-10-30 12:16:21 -07:00
1abd6bca42
Merge branch 'master' into master
2022-10-27 10:18:59 -07:00
67a77d863e
Update dpram.v
2022-10-27 08:29:56 +03:00
0fe3bd36b6
Update dpram16k.v
2022-10-27 08:28:58 +03:00
74568b13a2
Update dpram1k.v
2022-10-26 16:32:14 +03:00
64b5b5c31c
Update dpram_2048x8.v
2022-10-26 16:31:16 +03:00
f8b170ba75
Update dpram16k.v
2022-10-26 16:27:30 +03:00
82d8630ed4
Merge branch 'master' into patch-3
2022-10-24 13:32:42 +03:00
40f1f2fbc6
[test] update golden results for iwls
2022-10-21 20:28:10 -07:00
04286508c8
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
2022-10-21 20:26:56 -07:00
62a437a3a1
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
db0e5dff93
Added new cell library for fracturable dsp36
...
Added new divisible 36x36 multiplier cell library for architectures which has fracturable dsp36:
- The 36x36 multiplier is form from sixteen 9x9 multipliers.
- It operates same modes with existing library. It can operate in 3 fracturable modes:
1. one 36-bit multiplier
2. two 18-bit multipliers
3. four 9-bit multipliers
- It provides ~%20 better area than existing cell library (mult_36x36.v)
Comparison made with Synopsys Design Compiler NXT:
mult_36x36.v Total cell area 20470 um2
frac_mult_36x36.v Total cell area 15103 um2
2022-10-21 17:30:20 +03:00
29d4b3cced
Update frac_mem_32k.v
...
1. Mixed use of non-blocking and blocking statements are unsynthesizable in Synopsys Design Compiler.
2. While defining a multidimensional array, the first array size is for the length and the second one is for the depth. The order for ram_a and ram_b arrays was wrong and it caused "out of bounds" error in DC.
2022-10-20 09:48:29 +03:00
00a485cbeb
[test] add missing file
2022-10-17 19:44:25 -07:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
8b00bfdff9
[test] replace hardcoded paths in task config files with relative paths
2022-10-17 11:55:57 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
e9ee039e60
Merge branch 'master' into rst_on_lut_strong
2022-10-13 16:01:57 -07:00
33e2b16cb1
[arch] fixed a bug which caused verification failed
2022-10-13 15:33:43 -07:00
1c36ac28f1
[arch] code format
2022-10-13 12:17:32 -07:00
32f48f16c7
[arch] fixed a few bugs
2022-10-13 11:54:58 -07:00
b0be27b384
[test] add repack design constraints files
2022-10-13 11:22:48 -07:00
5cf315958d
[test] deploy new test to basic regression tests
2022-10-13 11:17:34 -07:00
7b7217d116
[arch]add new arch to test
2022-10-13 11:08:51 -07:00
7f67794787
[arch]add new arch to test
2022-10-13 10:54:40 -07:00
d7a253408d
Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 14:00:59 +03:00
6f55371d4b
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 13:53:32 +03:00
f62d435b1e
Update frac_mem_32k.v
2022-10-12 09:35:35 +03:00
35869b480a
Merge branch 'master' into xmllint
2022-10-07 10:47:43 -07:00
85089cbc88
[arch] apply xml format for all the architecture files
2022-10-07 10:31:51 -07:00
508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-07 09:38:07 +03:00
ab53f88c2b
[test] now use a fixed device layout for the single-mode LUT design testcase
2022-10-04 10:05:22 -07:00
13c819bb28
[ci] deply new test to ci
2022-10-01 11:04:08 -07:00
4eaecde0b9
[test] add golden netlists to ensure no cout in gsb
2022-10-01 11:03:13 -07:00
78f30cf072
[test] add a new test to track the golden netlists where cout is not in GSB
2022-09-30 15:38:27 -07:00
0d8d8446ee
[test] fixed a bug where OPIN for direct connection is included in GSB
2022-09-30 15:24:51 -07:00
088ff1a474
[script] fixed a bug
2022-09-29 16:27:03 -07:00
0565ca7aca
[script] add missing files
2022-09-29 16:14:38 -07:00
a3e7133d63
Merge branch 'master' into wire_lut_test
2022-09-29 16:02:18 -07:00
2ed4a60f36
[arch] reduce clb inputs to force net remapping during routing
2022-09-29 15:52:30 -07:00
ce0fbe1765
[test] fixed a few bugs
2022-09-29 15:32:31 -07:00
9bc9b61d35
[test] fixed a few bugs
2022-09-29 15:11:30 -07:00
f5e7ec4dd1
[test] add a new test case to validate wire lut case
2022-09-29 14:28:59 -07:00
df1ae7ba2a
[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
2022-09-29 14:23:17 -07:00
f7a02422b5
[arch] add a new arch to reproduce the wire-lut bug in repacker
2022-09-29 13:59:08 -07:00
3f8e2ade2e
[script] update missing scripts required by pb_pin_fixup test cases
2022-09-29 13:39:46 -07:00
49fa783914
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00
79b260f5e1
[arch] update missing arch
2022-09-21 16:52:32 -07:00
b1f8cdab3c
[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
2022-09-21 15:28:56 -07:00
eaa0b5588a
[test] fixed a bug in pin constrain examples
2022-09-21 14:10:12 -07:00
b532bca9d2
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
2022-09-21 10:54:16 -07:00
baac236ed7
[test] fixed a bug in example scripts due to the changes on vpr options
2022-09-21 10:52:49 -07:00
d0b018ad6e
[script] mismatches in vpr options due to upgrade
2022-09-21 09:27:26 -07:00
40edf859e3
Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-20 22:38:06 -07:00
97f0445787
[arch] upgrade arch file which was designed for v1.1
2022-09-20 22:37:35 -07:00
36603f9772
Merge branch 'master' into vtr_upgrade
2022-09-20 21:08:06 -07:00
e0f632cc9c
[test] fixed a bug
2022-09-20 20:29:34 -07:00
645d8df7b9
[test] fixed a bug
2022-09-20 20:09:41 -07:00
9042fc2422
[test] now reg test should show diff details when failed
2022-09-20 19:32:34 -07:00
b8f1520367
[test] fixed a bug
2022-09-20 18:12:23 -07:00
4e254a304d
[test] now golden netlists have no relationship with OPENFPGA_PATH
2022-09-20 18:10:52 -07:00
5e23be19a5
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
2022-09-20 18:07:31 -07:00
1b0b50b928
[test] update golden netlist
2022-09-20 16:04:05 -07:00
a137f7148c
[arch] fixed a bug
2022-09-20 15:47:15 -07:00
da157ed5de
[test] debugging git-diff
2022-09-20 15:31:39 -07:00
3f8106f12e
[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
2022-09-20 15:19:32 -07:00
b630d60b7e
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
2022-09-20 14:14:18 -07:00
6a896a9845
[test] debugging
2022-09-20 14:08:22 -07:00
ecfdc4a83a
[test] debugging
2022-09-20 13:51:32 -07:00
abee802830
[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
2022-09-20 13:46:30 -07:00
bdcdc7d294
[test] Now git diff in basic regression tests should capture the changes on golden outputs
2022-09-20 13:36:31 -07:00
37c5056d6a
[test] now use a fixed routing channel width for quicklogic tests
2022-09-20 12:25:40 -07:00
846ca26311
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
2022-09-20 12:08:24 -07:00
b3449a338f
[arch] update out-of-date vpr arch from v1.1 to v1.2
2022-09-20 09:51:43 -07:00
63cb8d589d
[test] fixed a typo
2022-09-19 23:14:15 -07:00
40663f956c
[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
2022-09-19 21:55:15 -07:00
d9bd0a6cf3
[test] disable clustering-routing result sync-up when calling vpr in example scripts
2022-09-19 20:52:04 -07:00
fca1c82388
[test] disable clustering and routing sync when using VPR
2022-09-19 20:33:35 -07:00
373566416c
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-16 16:47:21 -07:00
a8d7b6c2c4
[script] add a python script for users to visualize the I/O sequence
2022-09-16 10:49:10 -07:00
a2e22787c2
[test] deploy the new test cases to the basic regression tests
2022-09-16 10:31:15 -07:00
10e86d334a
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
2022-09-16 10:29:19 -07:00
f2e13e5ea9
[arch] add more flexible layout to test I/O center features
2022-09-16 10:00:08 -07:00
ec38b3990f
[arch] update to check OpenFPGA I/O indexing
2022-09-14 13:58:12 -07:00
83c89ae1bf
[arch] add more corner case to test the custom I/O location feature
2022-09-13 23:05:41 -07:00
330785635d
[test] now use a bigger fabric for the test case on custom I/O location
2022-09-13 17:53:33 -07:00
a37e270f25
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
2022-09-13 16:57:18 -07:00
1c2192a87d
[engine] fixed a few bugs
2022-09-12 16:50:32 -07:00
0d6e4e3979
[test] add a new example for the repack options
2022-09-12 16:21:49 -07:00
a3d070ac6f
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
2022-09-12 10:43:21 -07:00
314f5395b4
[benchmark] fixed a bug which causes yosys failed
2022-09-09 17:04:59 -07:00
91fe27ff66
[test] deploy new test to ci
2022-09-09 17:00:28 -07:00
1ab7590603
[test] added a new test case to
2022-09-09 16:59:06 -07:00
cc974a80f7
[arch] added a new architecture to test the local routing architecture where reset is on LUT
2022-09-09 16:48:10 -07:00
7a38c7dd18
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
2022-09-09 16:42:55 -07:00
95d7a17b3c
Merge branch 'master' into vtr_upgrade
2022-09-09 14:32:42 -07:00
d4523e819c
[test] fixed a bug
2022-09-08 16:55:50 -07:00
419a3a1e46
[arch] fixed a bug
2022-09-08 16:53:52 -07:00
122a323668
[arch] fixed bugs
2022-09-08 16:50:33 -07:00
d76f3e3b6c
[test] fixed the bug
2022-09-08 16:34:23 -07:00
218e6d0a47
[arch] fixed syntax errors
2022-09-08 16:31:52 -07:00
a840aeea7a
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
2022-09-08 16:27:11 -07:00
b1fad0b4e5
[arch] add an example architecture to show the use extended syntax
2022-09-08 16:19:21 -07:00
56619f9a47
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-07 15:04:05 -07:00
477e2119d7
[test] remove abs paths in golden outputs without time stamps
2022-09-06 15:24:43 -07:00
93ab992187
[test] update golden outputs without time stamps
2022-09-06 14:59:00 -07:00
561d0a6545
[test] add more test case to track golden outputs for representative fpga sizes
2022-09-06 14:04:23 -07:00
9e1abf5898
Merge branch 'master' into vtr_upgrade
2022-09-01 21:39:14 -07:00
c48f750f86
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
2022-09-01 20:10:29 -07:00
c691eb0e95
Merge branch 'master' into vtr_upgrade
2022-09-01 15:54:14 -07:00
51dc082bd4
[test] force a fixed routing chan W for no time stamp test case
2022-09-01 15:02:40 -07:00
d86eb04c5d
[test] now no timestamp test case covers gsb files
2022-09-01 14:03:51 -07:00
71ad0721a1
Merge branch 'master' into vtr_upgrade
2022-08-31 13:56:17 -07:00
201bca8968
[test] typo
2022-08-30 08:59:20 -07:00
5f88b9a226
[test] typo
2022-08-29 22:41:15 -07:00
0b5bdcdbb1
[test] deploy new test to basic regression tests
2022-08-29 22:07:56 -07:00
069e2b00b1
[test] add more test cases to validate gsb options
2022-08-29 22:03:06 -07:00
dbacee8a0a
[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
2022-08-27 20:25:50 -07:00
ef3381a1b2
[script] also turn off pb_pin_fixup in vpr for quicklogic tests
2022-08-27 20:07:49 -07:00
b9fade4c76
[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
2022-08-27 20:04:29 -07:00
e9d6e7e38a
[engine] update vtr and enable more debugging info
2022-08-27 19:12:43 -07:00
8d6682c28b
[test] fixed a bug when removing previous runs
2022-08-25 16:20:18 -07:00
fa790d50d4
[script] fixed a bug on wrong path to the ace2 executable
2022-08-23 10:53:44 -07:00
bdb051f787
[arch] update arch files
2022-08-22 18:24:37 -07:00
6c44f321e5
[script] fixed a bug
2022-08-22 18:24:26 -07:00
2bbf2f02c9
[script] now return status on each arch upgrade task
2022-08-22 18:23:00 -07:00
b6e1175517
[script] update doc and avoid modify README.MD when updating arch files
2022-08-22 18:19:23 -07:00
8d45903dc2
[script] makefile for vpr arch
2022-08-22 18:13:48 -07:00
3c9c11d451
[script] working on formatting
2022-08-22 18:02:38 -07:00
55e765a206
[script] slight improve on formatting
2022-08-22 18:00:14 -07:00
4a7c3fce93
[script] debugging format
2022-08-22 17:04:30 -07:00
2f5ea0cabb
[script] functional arch file converter; need to clean up formatting issues
2022-08-22 16:40:49 -07:00
4efc506762
[script] now change to use minidom and debugging the child removal
2022-08-22 16:33:49 -07:00
880d7122bf
[script] complete code; start debugging on arch file converter
2022-08-22 12:29:49 -07:00
5134ea2233
[script] save progress
2022-08-22 11:00:46 -07:00
a61d6a2685
[script] developing arch converting script
2022-08-22 10:34:29 -07:00
c0b1d76a5e
[script] change default tool paths for OpenFPGA flow scripts
2022-08-18 11:02:21 -07:00
6ce1d4804c
[test] deploy new test case to basic regression tests
2022-08-01 21:05:05 -07:00
9ea4a7c90f
[script] fixed a bug
2022-08-01 19:18:41 -07:00
8b17bf1b1c
[test] add a new test case to validate that .act file is not required when power analysis flow is off
2022-08-01 18:44:47 -07:00
55c7b75ab6
[script] even when power analysis mode is turned off, if users define a act file, still use it
2022-08-01 18:13:57 -07:00
0da44ad1fc
[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
2022-08-02 08:02:28 +08:00
35fe858035
[test] fixed a few bugs
2022-07-28 12:06:16 -07:00
ca9122ddb9
[test] fixed a bug
2022-07-28 11:57:47 -07:00
ec31e124b7
[test] reworked test case on pcf2place
2022-07-28 11:51:56 -07:00
23f98d6a3b
[engine] fixed a few bugs
2022-07-26 13:55:29 -07:00
353de4546f
[test] add 'write_fabric_io_info' command to test cases
2022-07-26 13:48:54 -07:00
347a29f27c
Fix test name in basic regression test script.
2022-07-20 21:05:31 -07:00
3762a3aae4
Code clean up based on review.
2022-07-20 14:34:44 -07:00
cfc0d08060
Add constrain_pin_location command in openfpga; add full flow test.
2022-07-20 11:51:00 -07:00
4b9431b132
[test] avoid XML bitstream output when can go beyond github runners' disk space
2022-05-25 18:45:26 +08:00
9832722056
[test] now add QuickLogic memory bank to fpga bitstream regression tests
2022-05-25 11:42:32 +08:00
86347a9d49
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
2022-05-25 11:19:49 +08:00
7d694acf32
[test] debugging basic reg test paths
2022-05-23 11:21:36 +08:00
b41cbad5d3
[test] force to run git diff under root directory
2022-05-23 10:32:43 +08:00
488a934097
[test] give abs path for git diff in basic regression tests
2022-05-23 09:12:33 +08:00
0dc7caf3b7
[test] now regression test script supports remove all run dir through command-line options
2022-05-22 13:15:39 +08:00
751d87b8e3
[test] fix a bug in detect changes in golden netlists
2022-05-22 13:06:47 +08:00
6719a9aa26
[test] update golden netlists/testbenches etc.
2022-05-22 13:03:01 +08:00
17c4e9a1bb
Merge branch 'master' into binder
2022-05-10 19:58:17 -06:00
d7e854eae7
[test] deploy new test to ci
2022-05-09 17:23:57 +08:00
7ed1548c6e
[arch] fixed a few bugs
2022-05-09 17:22:48 +08:00
9f56e61342
[arch] syntax
2022-05-09 17:13:57 +08:00
0afe3a6d33
[HDL] update dff map rules to support negative triggered ffs
2022-05-09 16:58:18 +08:00
22c4d72358
[test] add a test case to validate negative edge-triggered ff
2022-05-09 16:57:42 +08:00
9c7868cfab
[hdl] add a counter design which is triggered by negative edges
2022-05-09 16:41:21 +08:00
812af4f722
[arch] add arch that supports negative edge triggered flip-flop
2022-05-09 16:32:01 +08:00
c8ff3fc8dc
[test] add regression test to validate compilation of openfpga cell library files
2022-05-09 16:00:51 +08:00
d4992fd9ad
[HDL] Add a multi-mode ff which can support posedge and negedge
2022-05-09 15:52:17 +08:00
daae02a614
Minor documentation update
2022-05-08 13:03:16 -06:00
522982c9ba
Adde vtr_benchmarks_template for demo
2022-05-06 22:40:36 -06:00
9473523b6b
Added VTR arch without fracturable lut
2022-05-06 11:05:16 -06:00
275cda081e
[Bugfix] Typo
2022-05-05 08:40:21 -06:00
e845b62322
Update regession tasks
2022-05-05 01:46:19 -06:00
1e243650b9
Added option to copy example projects
2022-05-03 14:06:16 -06:00
21c3dbf611
Added regression for template project
2022-05-02 23:23:45 -06:00
9891e42f7a
Added template task
2022-05-02 11:49:16 -06:00
9bd66d531e
[Test] Deploy the new test case to basic regression tests
2022-04-13 16:06:27 +08:00
efc25aa66e
[Script] Fixed a bug in wrong paths
2022-04-13 16:04:33 +08:00
5beefda3bd
[Test] Add a new test case to validate the fix_pins option
2022-04-13 15:55:21 +08:00
576b9c2d8f
[Script] Disable SDC writer in multiclock examples
2022-03-20 11:05:29 +08:00
3e3a65223c
[Test] Deploy new test case to basic regression tests
2022-03-20 11:04:07 +08:00
f8845f7d3a
[Test] Add a test case to validate separated clock pins in global port
2022-03-20 11:02:07 +08:00
c8da85cc24
[Doc] Update naming convention for OpenFPGA architecture files
2022-03-20 10:51:55 +08:00
a1e2d9c864
[Arch] Add a new example openfpga arch where clock ports are independent
2022-03-20 10:50:31 +08:00
9f7a182433
[Arch] Typo
2022-02-24 09:51:26 -08:00
fdaf97e60d
[Test] Update test case by using GPIO with config_done signals
2022-02-24 09:49:34 -08:00
fcaff28e24
[HDL] Add a new IO cell with config_done support
2022-02-24 09:46:55 -08:00
a615c9d4e3
[Test] Rename test cases
2022-02-24 09:43:41 -08:00
e443a4567d
[Arch] Typo
2022-02-23 22:09:26 -08:00
b27a04eb24
[Test] Now test case has a config done CCFF
2022-02-23 22:07:11 -08:00
cf31879b20
[Test] Deploy new test to basic regression tests
2022-02-23 16:03:56 -08:00
245c7b1e45
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
2022-02-23 16:02:00 -08:00
e33ba667e4
[Test] Add missing file
2022-02-20 10:59:44 -08:00
f30de1085c
[Test] Cover all the related testcase about bus group
2022-02-19 23:33:16 -08:00
b4202f52b4
[Test] debugging
2022-02-19 23:26:29 -08:00
785bb1633d
[Test] trying to see if we support busgroup per benchmark in task configuration file
2022-02-19 23:23:36 -08:00
7645d5332d
[Test] Update bug group examples on the big endian support
2022-02-18 23:09:03 -08:00
68644ea0f6
[Test] Add the new test to basic regression tests
2022-02-18 15:44:07 -08:00
f0ce1e79a3
[Test] Added a new test to validate bus group in full testbench
2022-02-18 15:43:21 -08:00
fe9e0ff977
[Test] Add the new test to basic regression tests
2022-02-18 15:38:53 -08:00
c897a64ad5
[Script] Add a new example script to test full testbenches using bus group features
2022-02-18 15:37:42 -08:00
223575cf3e
[Test] Added a new test for bus group on full testbenches
2022-02-18 15:33:29 -08:00
85c893c94c
[Test] Add new test to basic regression tests
2022-02-18 15:30:08 -08:00
5ab84e1861
[Test] Add a new test for bus group
2022-02-18 15:29:33 -08:00
b4d59fdd1e
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
2022-02-18 15:02:08 -08:00
36543f7f2f
[Script] Support simplified rewriting for Yosys on output verilog
2022-02-18 14:54:39 -08:00
8ba3d06392
[Test] Fixed bugs in simulation settings
2022-02-18 12:36:22 -08:00
a4d5172b7c
[Test] Fixed bugs that causes VPR failed
2022-02-18 12:31:29 -08:00
43d852d8a1
[Test] Add the bus group test case to basic regression tests
2022-02-18 12:27:25 -08:00
7176037bc4
[Test] Added a new test about bus group
2022-02-18 12:26:00 -08:00
73e6ee964d
[Script] Add a new example script showing how to use bus group features
2022-02-18 12:25:34 -08:00
f02f3c10d4
[Test] Fix bugs on the remaining implicit verilog test cases
2022-02-15 16:49:15 -08:00
074811a612
[Script] Now counter benchmarks should pass on the implicit verilog test case
2022-02-15 16:47:14 -08:00
1370be0817
[Script] Fixing bugs
2022-02-15 16:44:51 -08:00
8be0868a3b
[Test] Update test case which uses counter benchmarks: adding pin constraints
2022-02-15 16:29:06 -08:00
430580f138
[HDL] Fix a typo
2022-02-15 16:09:14 -08:00
a7786efde1
[HDL] Now dual-clock counter has only 1 reset pin
2022-02-15 16:07:50 -08:00
f002c79a61
[Test] Adapt pin constraints due to changes in pin names
2022-02-15 16:06:46 -08:00
b533fd17d5
[Test] Rework pin constraints that cause problems
2022-02-15 15:41:16 -08:00
9ef7ad64d8
[Test] Simplify paths
2022-02-15 15:35:21 -08:00
7121513396
[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
2022-02-15 15:21:08 -08:00
74045fc7a1
[Script] Fix a bug
2022-02-14 23:11:42 -08:00
2990eb7406
[Script] Fixed a bug in task run when removing previous runs
2022-02-14 22:54:16 -08:00
d0fe8d96fa
[Test] Update template scripts and assoicated test cases by offering more options
2022-02-14 16:03:48 -08:00
d667102a43
[Test] Add new test case to regression tests
2022-02-14 15:58:53 -08:00
70363effa4
[Test] Add a new test to validate 8-bit counters using full testbenches
2022-02-14 15:57:55 -08:00
2fb1df11bb
[Script] Add a new example script
2022-02-14 15:54:07 -08:00
7ef808cbe4
[Test] Update pin constraints for different counter benchmarks
2022-02-14 15:28:03 -08:00
570c1b10dc
[Test] Add dedicated pin constraints for counter designs
2022-02-14 13:54:48 -08:00
85011824e2
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
2022-02-14 13:15:55 -08:00
6630c17c23
[Test] Use preconfigured testbench template to run counter8 tests
2022-02-14 13:07:31 -08:00
da3f9ccb80
[Test] Truncating counter designs in each task
2022-02-14 12:22:19 -08:00
0268814fc6
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
2022-02-14 12:20:56 -08:00
1d3c9ff192
[Script] Adapt python scripts to support include directory
2022-02-01 13:55:25 -08:00
27ac2fafe5
[Test] Add the new test case to regression tests
2022-02-01 13:45:46 -08:00
532af96243
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
2022-02-01 13:44:47 -08:00
35c7968c98
[Script] Add a new example openfpga shell script
2022-02-01 13:40:22 -08:00
09ef516de8
[Script] Tune OpenFPGA shell script to enable testing on relative paths
2022-01-31 14:23:13 -08:00
9871fe88fb
[Test] Typo fix
2022-01-31 13:03:45 -08:00
da8fc0f5d4
[Test] Add a new test case to validate ``--use_relative_path``
2022-01-31 13:02:19 -08:00
e59ea91ad6
[Script] Fixed a bug which causes errors
2022-01-26 11:49:32 -08:00
f8ef3df560
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
2022-01-26 11:41:48 -08:00
a9042318cf
[Test] Deploy the test case to regression tests
2022-01-26 11:26:17 -08:00
3b7588cd48
[Test] Rename test case to be consistent with the name of options
2022-01-26 11:25:54 -08:00
6b26ed0819
[Test] Add test cases on writing gsb files
2022-01-26 11:22:39 -08:00
5db049522d
[Script] Add an example script about write GSB
2022-01-26 11:22:23 -08:00
11e045992d
[Test] Now only compare on the golden netlist changes to branch
2022-01-25 21:24:10 -08:00
23795d6474
[Test] Update golden netlists
2022-01-25 20:37:08 -08:00
a9e6b7c12e
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
2022-01-25 20:33:49 -08:00
c2c827ee10
[Script] Fix a bug in git-diff for regression tests
2022-01-25 20:27:41 -08:00
fedb1bd2e3
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
2022-01-25 16:41:36 -08:00
5c0f63ddd9
[Test] Update regression tests for the new test about ``--no_time_stamp``
2022-01-25 16:30:48 -08:00
6e778a74ee
[Test] Add golden reference for files outputted without time stamp
2022-01-25 16:24:25 -08:00
2bee59c6ca
[Test] Add the testcase to validate ``--no_time_stamp``
2022-01-25 16:21:15 -08:00
dd803dd1de
[Test] Remove unused tests
2022-01-25 16:16:58 -08:00
e4cfa2222f
[Script] Add an example script to test option ``--no_time_stamp``
2022-01-25 16:16:39 -08:00
dd40057992
[Script] Fixed a bug which causes errors when removing run-directory
2022-01-25 13:56:42 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
397f2e71f1
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
2022-01-19 20:43:26 +05:00
bd158311c5
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
2022-01-18 14:07:41 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
fb2e4377c8
Added missing changes from previous commit.
2022-01-17 19:42:40 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
469b3a960c
basic reg test updated
2022-01-14 15:44:26 +05:00
793e40cb95
basic_reg test for yosys-only flow added in OpenFPGA regression test scripts
2022-01-14 15:39:26 +05:00
598c5e6b75
Test case for yosys-only flow added
2022-01-14 15:37:47 +05:00
fc52a4696c
Yosys only support added in OpenFPGA
2022-01-06 14:44:11 +05:00
27caeb1d1f
[Arch] Patched VPR arch
2022-01-02 20:47:22 -08:00
384a1e58d6
[Arch] Patch architecture using DSP with registers
2022-01-02 20:44:43 -08:00
e3baec63f8
[Arch] Bug fix on architecture with registerable DSP
2022-01-02 20:35:48 -08:00
f667065f75
[Arch] Bug fix in DSP with registers architecture
2022-01-02 20:34:26 -08:00
9c476ed5db
[Arch] Syntax error fix
2022-01-02 20:27:00 -08:00
628191da5f
[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests
2022-01-02 20:21:58 -08:00
824a03bdca
[Flow] Patch new test case
2022-01-02 20:20:36 -08:00
48355d1fc3
[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers
2022-01-02 20:16:59 -08:00
55da99f4ca
[Flow] Add a new test case to validate DSP with registers
2022-01-02 20:08:23 -08:00
62b4a0b7ff
[Flow] Add openfpga arch for DSP with registers
2022-01-02 19:59:33 -08:00
7598455497
[Doc] Update naming convention for architecture files
2022-01-02 19:51:09 -08:00
48491fcf52
[Flow] Add example architecture for DSP with input and output registers
2022-01-02 19:47:39 -08:00
81966c2131
[Doc] Update README for DSP blocks
2022-01-02 18:27:37 -08:00
236910cde4
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-12-09 00:00:21 +05:00
06fb4b0ece
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-25 00:00:22 +05:00
3c14373abf
revert unnecessary task.conf changes
2021-11-19 19:07:09 +05:30
9ca8ab4fa2
minor change to task.conf to check CI
2021-11-19 18:49:37 +05:30
b86bd1ca68
re-enable counter_5clock,sdc_controller, lut_adder tests
2021-11-19 18:06:06 +05:30
31379062e3
remove minor comments
2021-11-18 18:40:15 +05:30
1ea56b2d18
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-18 00:00:55 +05:00
91094305bd
enable all tests except 15 and 19
2021-11-17 20:56:12 +05:30
fe74c42252
Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure
2021-11-12 01:46:06 -08:00
840fa399c6
enable single counter test (fails, needs debug)
2021-11-09 21:36:33 +05:30
3fa373f8bc
add plugins, set yosys install for plugin
2021-11-04 07:22:09 +05:30
a707226ba6
Added 'basic_tests/verific_test' test case into regression tests suite.
2021-11-01 18:33:33 +05:00
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
ff264c00a2
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-31 11:51:34 -07:00
0d882f57b1
Merge branch 'master' into yosys+verific_support
2021-10-30 22:49:21 -07:00
0d14aa4cb8
[Flow] Add comments to clarify the limitations
2021-10-30 19:17:11 -07:00
7f999d03c6
[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
2021-10-30 18:05:39 -07:00
370e3fef83
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
2021-10-30 18:03:59 -07:00
7455990ead
[Flow] bug fix
2021-10-30 16:52:32 -07:00
c8e9dfbeda
[Test] bug fix
2021-10-30 16:50:57 -07:00
27b82d1473
[Flow] bug fix
2021-10-30 16:09:31 -07:00
a4cfc84930
[Test] Bug fix
2021-10-30 16:00:47 -07:00
335347a74f
[Test] Bug fix
2021-10-30 15:48:25 -07:00
6277234125
[Flow] bug fix in BRAM-oriented yosys scripts
2021-10-30 15:34:30 -07:00
be47e78289
[Arch] Change arch for Sapone test
2021-10-30 15:23:19 -07:00
e6cc3c4942
[Flow] Enable flatten for dff-related yosys scripts
2021-10-30 15:12:34 -07:00
ad5cce0ae8
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
2021-10-30 15:11:07 -07:00
8dea7e80e6
[Flow] Update yosys script to not use sdff and dffe
2021-10-30 14:56:54 -07:00
40d11a45d9
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
2021-10-30 14:49:56 -07:00
b7ad61227d
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
2021-10-30 14:47:37 -07:00
ec184ef532
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
2021-10-30 14:46:12 -07:00
0b770f3330
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 14:36:43 -07:00
59a622a910
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 14:34:37 -07:00
978c60e75b
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 13:29:38 -07:00
18bab18032
[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
2021-10-30 13:20:58 -07:00
16de60e943
[Test] Turn off ACE2 run in bitstream generation only flows
2021-10-30 12:31:14 -07:00
94328351be
[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
2021-10-30 12:00:06 -07:00
0a449cc24c
[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
2021-10-30 11:45:01 -07:00
9c06041ce4
[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
2021-10-30 11:27:40 -07:00
a355977420
Adding Yosys+Verific support.
2021-10-29 18:34:27 +05:00
b8d5920529
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-28 15:45:58 -07:00
2eef21a1af
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
274252438a
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-10-20 20:13:46 +05:00
c42acec81e
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
2021-10-18 10:45:35 +00:00
c3dd704bf3
Fixing typo in run_fpga_flow.py
2021-10-18 09:13:42 +00:00
d411967159
Fixing small typo in run_fpga_flow.py
2021-10-15 10:01:12 +00:00
e0cfd46ec7
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-10-14 19:25:31 +05:00
b2c4e3314e
[Test] Bug fix in test cases
2021-10-11 10:28:09 -07:00
8566e2a0cd
[Test] Renaming test case to follow naming convention as other fabric key test cases
2021-10-11 09:56:23 -07:00
2bf203cd00
[Test] Deploy the new test to basic regression test
2021-10-11 09:54:39 -07:00
b8b02d37d5
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
2021-10-11 09:53:23 -07:00
cdcb07256b
[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization
2021-10-11 09:49:22 -07:00
982a324e0d
[Test] Temporarily disable some tests; Will go back later
2021-10-10 23:30:50 -07:00
40fd89fdb4
[arch] Update fabric key for multi-region
2021-10-10 22:03:49 -07:00
8f9e564cd5
[Test] Add the new test to basic regression test
2021-10-09 20:45:23 -07:00
6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
82e77b42c5
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
2021-10-09 20:43:55 -07:00
8aa2647878
[Script] Bug fix in slow clock frequency in shift register chain contraints
2021-10-06 16:49:01 -07:00
dc5aedc393
[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
2021-10-06 13:36:35 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
554018449e
[Test] Update regression test script
2021-10-06 12:10:37 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
169bb5fa45
[Script] Add an example simulation setting file with a fixed clock frequency for shift registers
2021-10-06 11:58:50 -07:00
189ade6c1e
[Test] Bug fix
2021-10-05 19:17:34 -07:00
f74ea5d39a
[Test] Use the new openfpga shell script in don't care bit tests
2021-10-05 19:14:44 -07:00
4add9781d5
[Script] Add a new openfpga shell script for don't care bits outputting
2021-10-05 19:13:50 -07:00
50604e4589
[Test] move test cases
2021-10-05 19:02:43 -07:00
064ac478f3
[Test] Deploy news test to fpga-bitstream regression tests
2021-10-05 19:01:03 -07:00
fed6c133b1
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
2021-10-05 18:59:33 -07:00
80fd1efd61
[Test] Add an example test key for multi-region QuickLogic memory bank using shift registers
2021-10-05 11:46:58 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
492db50efe
[Test] Deploy the new test to basic regression tests
2021-10-05 10:59:26 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
d2859ca1c8
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
2021-10-05 10:56:20 -07:00
fbef22b494
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
2021-10-04 16:39:53 -07:00
13c31cb89c
[Test] Deploy the qlbanksr_wlr to basic regression tests
2021-10-04 16:37:49 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
7f75c2b619
[Test] Deploy shift register -based QL memory bank test case to basic regression test
2021-10-03 16:06:44 -07:00
86e7c963f8
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
2021-10-02 22:19:20 -07:00
0b06820177
[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
2021-10-01 17:06:35 -07:00
7ba5d27ea7
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
2021-10-01 17:02:35 -07:00
ff6f7e80f6
[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
2021-10-01 16:52:06 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
7b010ba0f4
[Engine] Support programming shift register clock in XML syntax
2021-10-01 11:00:38 -07:00
fa57117f50
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
2021-10-01 10:19:51 -07:00
41cc375746
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
2021-09-29 16:34:40 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4968f0d11f
Merge branch 'master' into qlbank_sr
2021-09-28 14:20:30 -07:00
80232fc459
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
2021-09-28 12:36:36 -07:00
4c04c0fbd7
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
2021-09-28 12:35:42 -07:00
2ce2fb269a
[HDL] Added a different FF model which is designed to drive WLW only
2021-09-28 12:35:13 -07:00
6469ee3048
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
2021-09-28 12:21:54 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
4aed045cdd
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
2021-09-28 11:34:20 -07:00
811c898173
[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
2021-09-28 11:29:45 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
1ca1b0f3e9
[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
2021-09-22 15:58:05 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
a98df811ed
[Arch] Bug fix: wrong circuit model name was used for CCFF
2021-09-22 15:50:47 -07:00
53da5d49fe
[Arch] Correct XML syntax errors
2021-09-22 15:48:14 -07:00
3cfd5c3531
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
2021-09-22 15:04:59 -07:00
212c5bd642
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
2021-09-22 15:04:19 -07:00
tangxifan
Yunus Emre ERYILMAZ
mustafa.arslan
root
taoli4rs
ganeshgore
Aram Kostanyan
Awais Abbas
nadeemyaseen-rs
coolbreeze413
Lalit Sharma
Christophe Alexandre