[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
This commit is contained in:
parent
b3449a338f
commit
846ca26311
|
@ -2,7 +2,8 @@
|
|||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on
|
||||
# Enable block usage in log file, otherwise QoR check in OpenFPGA flow-run will fail
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
|
@ -2,7 +2,8 @@
|
|||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on
|
||||
# Enable block usage in log file, otherwise QoR check in OpenFPGA flow-run will fail
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
|
@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
|
|||
# VPR parameters
|
||||
# Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=300
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
|
||||
|
|
|
@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
|
|||
# VPR parameters
|
||||
# # Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=60
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
|
||||
|
|
|
@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
|
|||
# VPR parameters
|
||||
# Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=300
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
|
||||
|
|
|
@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
|
|||
# VPR parameters
|
||||
# Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=300
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
|
||||
|
|
|
@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
|
|||
# VPR parameters
|
||||
# Use a fixed routing channel width to save runtime
|
||||
vpr_route_chan_width=300
|
||||
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
|
||||
|
|
Loading…
Reference in New Issue