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[Test] Fix bugs on the remaining implicit verilog test cases

This commit is contained in:
tangxifan 2022-02-15 16:49:15 -08:00
parent 074811a612
commit f02f3c10d4
2 changed files with 8 additions and 1 deletions
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7
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/pin_constraints_reset.xml Normal file
View File

@ -0,0 +1,7 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="reset[0]" net="rst_counter"/>
</pin_constraints>

2
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
View File

@ -30,7 +30,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = counter
bench0_chan_width = 300
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=