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[Script] Now counter benchmarks should pass on the implicit verilog test case

This commit is contained in:
tangxifan 2022-02-15 16:47:14 -08:00
parent 1370be0817
commit 074811a612
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
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@ -57,7 +57,7 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Write the SDC files for PnR backend
# - Turn on every options here