diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
index f7ab0e145..698b25ec3 100644
--- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
@@ -57,7 +57,7 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
 write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here