[hdl] add a counter design which is triggered by negative edges

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v

@@ -0,0 +1,29 @@
+///////////////////////////////////////////
+//  Functionality: Counter triggered at negative edge with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clkn,
+	reset,
+	result
+);
+
+	input clkn;
+	input reset;
+	output [7:0] result;
+
+	reg [7:0] result;
+
+    initial begin
+      result <= 0;
+    end
+
+	always @(negedge clkn or posedge reset)
+	begin
+		if (reset) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v

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+module counter_tb;
+
+  reg clk, reset;
+  wire [7:0] result;
+
+  counter DUT(
+    .clkn(clk), 
+    .reset(reset), 
+    .result(result)
+  );
+  
+  initial begin
+    #0 reset = 1'b1; clk = 1'b0;
+    #100 reset = 1'b0;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+  
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule