From 9c7868cfabe0c0cd702909d43c529518b13fc757 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 May 2022 16:41:21 +0800
Subject: [PATCH] [hdl] add a counter design which is triggered by negative
 edges

---
 .../counter.v                                 | 29 +++++++++++++++++++
 .../counter_tb.v                              | 25 ++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v
new file mode 100644
index 000000000..12d22e61e
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v
@@ -0,0 +1,29 @@
+///////////////////////////////////////////
+//  Functionality: Counter triggered at negative edge with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clkn,
+	reset,
+	result
+);
+
+	input clkn;
+	input reset;
+	output [7:0] result;
+
+	reg [7:0] result;
+
+    initial begin
+      result <= 0;
+    end
+
+	always @(negedge clkn or posedge reset)
+	begin
+		if (reset) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v
new file mode 100644
index 000000000..566ba3ed7
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v
@@ -0,0 +1,25 @@
+module counter_tb;
+
+  reg clk, reset;
+  wire [7:0] result;
+
+  counter DUT(
+    .clkn(clk), 
+    .reset(reset), 
+    .result(result)
+  );
+  
+  initial begin
+    #0 reset = 1'b1; clk = 1'b0;
+    #100 reset = 1'b0;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+  
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule