[HDL] Fix a typo

2022-02-15 16:09:14 -08:00 · 2022-02-15 16:09:14 -08:00 · 430580f138
parent a7786efde1
commit 430580f138
1 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v
@ -1,4 +1,4 @@
-module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
+module counter_4bit_2clock(clk0, rst, clk1, q0, q1);

    input clk0;
    input rst;