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[Arch] Patched VPR arch

This commit is contained in:
tangxifan 2022-01-02 20:47:22 -08:00
parent 384a1e58d6
commit 27caeb1d1f
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
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@ -342,9 +342,9 @@
<output name="OUT_cfg" num_pins="16"/>
<clock name="clk" num_pins="1"/>
<pb_type name="mult_8x8" blif_model=".subckt mult_8" num_pb="1">
<input name="A" num_pins="36"/>
<input name="B" num_pins="36"/>
<output name="Y" num_pins="72"/>
<input name="A" num_pins="8"/>
<input name="B" num_pins="8"/>
<output name="Y" num_pins="16"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.A" out_port="mult_8x8.Y"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.B" out_port="mult_8x8.Y"/>
</pb_type>