From 27caeb1d1f313b77aaa37d815558a7a2800b1d35 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 2 Jan 2022 20:47:22 -0800
Subject: [PATCH] [Arch] Patched VPR arch

---
 openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
index 7c102ae3c..6016412ab 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
@@ -342,9 +342,9 @@
           <output name="OUT_cfg" num_pins="16"/>
           <clock name="clk" num_pins="1"/>
           <pb_type name="mult_8x8" blif_model=".subckt mult_8" num_pb="1">
-            <input name="A" num_pins="36"/>
-            <input name="B" num_pins="36"/>
-            <output name="Y" num_pins="72"/>
+            <input name="A" num_pins="8"/>
+            <input name="B" num_pins="8"/>
+            <output name="Y" num_pins="16"/>
             <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.A" out_port="mult_8x8.Y"/>
             <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.B" out_port="mult_8x8.Y"/>
           </pb_type>