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re-enable counter_5clock,sdc_controller, lut_adder tests

This commit is contained in:
coolbreeze413 2021-11-19 18:06:06 +05:30
parent e9468eedbf
commit b86bd1ca68
1 changed files with 6 additions and 8 deletions
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14
openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh
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@ -8,14 +8,12 @@ PYTHON_EXEC=python3.8
##############################################
echo -e "QuickLogic regression tests";
# TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
run-task quicklogic_tests/flow_test --debug --show_thread_logs
##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
##
##echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
##run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs
echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
echo -e "Testing yosys flow using custom ys script for adders in quicklogic device";
run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs