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[Test] bug fix

This commit is contained in:
tangxifan 2021-10-30 16:50:57 -07:00
parent 27b82d1473
commit c8e9dfbeda
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf
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@ -9,7 +9,7 @@
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
power_analysis = false
spice_output=false
verilog_output=true
# Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement
@ -19,7 +19,7 @@ fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_route_chan_width=200
openfpga_vpr_device_layout=auto