From c8e9dfbedad116951a247db76a5c3de08df467cc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 Oct 2021 16:50:57 -0700
Subject: [PATCH] [Test] bug fix

---
 .../tasks/fpga_bitstream/repack_wire_lut/config/task.conf     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf
index 3c6c88b87..c4e3c9f42 100644
--- a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf
@@ -9,7 +9,7 @@
 [GENERAL]
 run_engine=openfpga_shell
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
 spice_output=false
 verilog_output=true
 # Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement
@@ -19,7 +19,7 @@ fpga_flow=vpr_blif
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_route_chan_width=200
 openfpga_vpr_device_layout=auto