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[script] also turn off pb_pin_fixup in vpr for quicklogic tests

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tangxifan 2022-08-27 20:07:49 -07:00
parent b9fade4c76
commit ef3381a1b2
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}