diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
index 92e52442c..e1f123224 100644
--- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} 
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}  --skip_sync_clustering_and_routing_results on
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}