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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade

This commit is contained in:
tangxifan 2021-10-30 18:05:39 -07:00
parent 370e3fef83
commit 7f999d03c6
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv
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@ -10,7 +10,7 @@ name,mult_blocks,memory_blocks
00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0
00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0
00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1
00_memset_MIN_ROUTE_CHAN_WIDTH,0,1
00_memset_MIN_ROUTE_CHAN_WIDTH,0,0
00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0
00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0
00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9
@ -20,7 +20,7 @@ name,mult_blocks,memory_blocks
00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3
00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3
00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2
00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1
00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,0
00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0
00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0
00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0

1 #####################################################################
10 00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0
11 00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0
12 00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1
13 00_memset_MIN_ROUTE_CHAN_WIDTH,0,1 00_memset_MIN_ROUTE_CHAN_WIDTH,0,0
14 00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0
15 00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0
16 00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9
20 00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3
21 00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3
22 00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2
23 00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1 00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,0
24 00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0
25 00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0
26 00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0