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Update dpram_2048x8.v

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Yunus Emre ERYILMAZ 2022-10-26 16:31:16 +03:00 committed by GitHub
parent f8b170ba75
commit 64b5b5c31c
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1 changed files with 2 additions and 2 deletions
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openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v
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@ -14,7 +14,7 @@ module dpram_2048x8 (
input[0:7] data_in,
output[0:7] data_out );
dual_port_sram memory_0 (
dpram_2048x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
@ -32,7 +32,7 @@ endmodule
// Function : Core module of dual port RAM 2048 addresses x 8 bit
// Coder : Xifan tang
//-----------------------------------------------------
module dual_port_sram (
module dpram_2048x8_core (
input wclk,
input wen,
input[0:10] waddr,