[test] added a new test to validate explicit port direction in pin table support
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tangxifan
parent
b82ebf2f23
commit
609e096b1a
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@ -1,5 +1,5 @@
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# Convert .pcf to a .place file that VPR can accept
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pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE}
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pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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@ -188,6 +188,7 @@ echo -e "Testing fix pins features";
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run-task basic_tests/io_constraints/fix_pins $@
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run-task basic_tests/io_constraints/example_pcf $@
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run-task basic_tests/io_constraints/empty_pcf $@
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run-task basic_tests/io_constraints/pcf_ql_style $@
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echo -e "Testing project templates";
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run-task template_tasks/vpr_blif_template $@
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@ -1,17 +1,17 @@
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orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
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TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
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TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
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RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
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RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
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BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
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BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
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LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
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LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
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TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
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TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
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TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
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TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
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TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
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TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
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TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
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TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
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RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
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RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
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RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
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RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
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BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
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BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
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LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
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LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
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@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
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openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_vpr_fix_pins_file=and2_fix_pins.place
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openfpga_pin_table_direction_convention=explicit
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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@ -1,17 +1,17 @@
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orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
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TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
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TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
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RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
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RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
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BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
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BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
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LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
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LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
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TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
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TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
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TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
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TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
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TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
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TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
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TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
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TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
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RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
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RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
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RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
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RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
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BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
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BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
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LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
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LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
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@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
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openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_vpr_fix_pins_file=and2_fix_pins.place
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openfpga_pin_table_direction_convention=explicit
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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@ -0,0 +1,3 @@
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set_io a pad_fpga_io[0]
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set_io b pad_fpga_io[4]
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set_io c pad_fpga_io[6]
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@ -0,0 +1,18 @@
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<io_coordinates>
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<io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
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<io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
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<io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
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<io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
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<io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
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<io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
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<io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
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<io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
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<io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
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<io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
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<io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
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<io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
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<io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
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<io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
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<io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
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<io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
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</io_coordinates>
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@ -0,0 +1,17 @@
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orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
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TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
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TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
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TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
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TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
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TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
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RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
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RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
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RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
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BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
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BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
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LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
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LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
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@ -0,0 +1,42 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=4x4
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openfpga_vpr_route_chan_width=20
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openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
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openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
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openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
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openfpga_vpr_fix_pins_file=and2_fix_pins.place
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openfpga_pin_table_direction_convention=quicklogic
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = and2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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