diff --git a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
index ad29fc51e..f25bf0323 100644
--- a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
@@ -1,5 +1,5 @@
 # Convert .pcf to a .place file that VPR can accept
-pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE}
+pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
 
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 221426609..e4bd6cff0 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -188,6 +188,7 @@ echo -e "Testing fix pins features";
 run-task basic_tests/io_constraints/fix_pins $@
 run-task basic_tests/io_constraints/example_pcf $@
 run-task basic_tests/io_constraints/empty_pcf $@
+run-task basic_tests/io_constraints/pcf_ql_style $@
 
 echo -e "Testing project templates";
 run-task template_tasks/vpr_blif_template $@
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv
index ba0691940..9b7206eba 100644
--- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv
@@ -1,17 +1,17 @@
 orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
-TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
-TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
-TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
-TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
-TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
-TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
-TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
-TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
-RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
-RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
-RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
-RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
-BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
-BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
-LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
-LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf
index b16acaecc..131d6246a 100644
--- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf
@@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
 openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
 openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
 openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=explicit
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv
index ba0691940..9b7206eba 100644
--- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv
@@ -1,17 +1,17 @@
 orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
-TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
-TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
-TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
-TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
-TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
-TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
-TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
-TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
-RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
-RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
-RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
-RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
-BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
-BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
-LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
-LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf
index b16acaecc..131d6246a 100644
--- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf
@@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
 openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
 openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
 openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=explicit
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf
new file mode 100644
index 000000000..839f8a857
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf
@@ -0,0 +1,3 @@
+set_io a pad_fpga_io[0]
+set_io b pad_fpga_io[4]
+set_io c pad_fpga_io[6]
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml
new file mode 100644
index 000000000..03eb56357
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml
@@ -0,0 +1,18 @@
+<io_coordinates>
+  <io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
+  <io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
+</io_coordinates>
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv
new file mode 100644
index 000000000..ba0691940
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv
@@ -0,0 +1,17 @@
+orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,,
diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf
new file mode 100644
index 000000000..cc57345e8
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf
@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
+openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
+openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
+openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=quicklogic
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=