[test] disable clustering and routing sync when using VPR

2022-09-19 20:33:35 -07:00 · 2022-09-19 20:33:35 -07:00 · fca1c82388
parent e19ca1c6d1
commit fca1c82388
1 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results off

 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}